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Communications Processor Module (CPM) Ports
General-
Purpose
1-20
Table 1-3. Port A Signals (Continued)
Name
Peripheral Controller:
Dedicated Signal
I/O
Protocol
PA29
FCC1: TXSOC
UTOPIA master
FCC1: TXSOC
UTOPIA slave
FCC1: TX_ER
MII
PA28
FCC1: RXENB
UTOPIA master
FCC1: RXENB
UTOPIA slave
FCC1: TX_EN
MII
PA27
FCC1: RXSOC
UTOPIA master
FCC1: RXSOC
UTOPIA slave
FCC1: RX_DV
MII
Dedicated
I/O Data
Direction
Output
FCC1: UTOPIA Transmit Start of Cell
In the ATM UTOPIA interface supported by FCC1. TXSOC
is asserted by the MSC8101 (UTOPIA master PHY) when
TXD[0–7] contains the first valid byte of the cell.
Input
FCC1: UTOPIA Transmit Start of Cell
In the ATM UTOPIA interface supported by FCC1. TXSOC
is asserted by the external UTOPIA master PHY when
TXD[0–7] contains the first valid byte of the cell.
Output
FCC1: Media Independent Interface Transmit Error
In the MII interface supported by FCC1. TX_ER is asserted
by the MSC8101 to force propagation of transmit errors.
Output
FCC1: UTOPIA Master Receive Enable
In the ATM UTOPIA interface supported by FCC1. (UTOPIA
master) RXENB is asserted by the MSC8101 (UTOPIA
master PHY) to indicate that RXD[0–7] and RXSOC are to
be sampled at the end of the next cycle. RXD[0–7] and
RXSOC are enabled only in cycles following those with
RXENB asserted.
Input
FCC1: UTOPIA Master Receive Enable
In the ATM UTOPIA interface supported by FCC1. (UTOPIA
slave) RXENB is an input asserted by an external PHY to
indicate that RXD[0–7] and RXSOC is to be sampled at the
end of the next cycle. RXD[0–7] and RXSOC are enabled
only in cycles following those with RXENB asserted.
Output
FCC1: Media Independent Interface Transmit Enable
In the MII interface supported by FCC1. TX_EN is asserted
by the MSC8101 when transmitting data.
Input
FCC1: UTOPIA Receive Start of Cell
Asserted by an external PHY when RXD[0–7] contains the
first valid byte of the cell.
Output
FCC1: UTOPIA Receive Start of Cell
Asserted by the MSC8101 (UTOPIA slave) for an external
PHY when RXD[0–7] contains the first valid byte of the cell.
Input
FCC1: Media Independent Interface Receive Data Valid
In the MII interface supported by FCC1. RX_DV is an input
asserted by an external fast Ethernet PHY. RX_DV
indicates that valid data is being sent. The presence of
carrier sense but not RX_DV indicates reception of broken
packet headers, probably due to bad wiring or a bad circuit.
Description
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