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Table 1-4.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
TEA
Input/Output
NMI
Input
NMI_OUT
Output
PSDVAL
Input/Output
IRQ7
Input
INT_OUT
Output
Notes:
1.
See the System Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to
configure these pins.
2.
When used as the bus control arbiter for the system bus, the MSC8101 can support up to three
external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant
signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3).
Each of these signal sets must be configured to indicate whether the external master is or is not a
MSC8101 master device. See the Bus Configuration Register (BCR) description in the System
Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to configure these
pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used
with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the
MSC8101 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8101 to obtain
master control of the bus.
3.
See the Host Interface (HDI16) chapter in the MCS8101 Reference Manual for details on how to
configure these pins.
System Bus, HDI16, and Interrupt Signals
Transfer Error Acknowledge
Indicates a bus error. masters within the MSC8101 monitor the state of this pin.
The MSC8101 internal bus monitor can assert this pin if it identifies a bus transfer
that is hung.
Non-Maskable Interrupt
When an external device asserts this line, the MSC8101 NMI input is asserted.
Non-Maskable Interrupt
Driven from the MSC8101 internal interrupt controller. Assertion of this output
indicates that a non-maskable interrupt, pending in the MSC8101 internal interrupt
controller, is waiting to be handled by an external host.
Data Valid
Indicates that a data beat is valid on the data bus. The difference between the TA
pin and PSDVAL is that the TA pin is asserted to indicate data transfer terminations
while the PSDVAL signal is asserted with each data beat movement. Thus, when
TA is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not
necessarily asserted. For example when the SDMA initiates a double word (2x64
bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted
three times without TA, and finally both pins are asserted to terminate the transfer.
1
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
1
Interrupt Output
Driven from the MSC8101 internal interrupt controller. Assertion of this output
indicates that an unmasked interrupt is pending in the MSC8101 internal interrupt
controller.
Description
1-15
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