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9100A-017
number of times the cycle is to be repeated. One output line of
the first module would be connected to the second module's DR
CLK line to clock out the address and data vectors (as shown in
Figure 7-5).
Figure 7-5. Connecting Two Modules for Timing Sets
The second module would contain the vector patterns to be out-
put on the address and data bus lines. The number of entries in
this vector file should be the same as the LOOP value set in the
first module's vector file.
The following example demonstrates this method:
7-20
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