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9100A Series
Service manual
Fluke 9100A Service Manual
9100 series computer system
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Also See for 9100A
:
Operation manual
(76 pages)
,
Manual
(122 pages)
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Table Of Contents
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Contents
Table of Contents
Bookmarks
Table of Contents
Contents
List of Tables
List of Figures
9100A System View
9105A System View
How to Use this Manual
This Manual
The Manual Set
Conventions
General Information
Description
Power Requirements
External Connections
Side Features
The 9100 Side View
The 9105A View, Showing Its Different Disk Drive Arrangement
Rear Panel Features View
9100A System Components
9105A System Components
Options
Accessories
Required Test Equipment
Shipping Information
Interface Pods
Required Tools and Test Equipment Table
Equipment Required for General Servicing
Required Equipment for Component Level Repair
Required Equipment for Monochrome Monitor Maintenance
Specifications
Electrical Specifications
Transition Counting
Clock Module Specifications
RS-232 Interfaces Specifications
I/O Module Specifications
Input Thresholds
Input Impedance
Stop Counter Specifications
Clock Specifications
Data Timing for Synchronous Measurements
Data Timing for Asynchronous Measurements
Data Compare Equal (DCE)
General Specifications
Theory of Operation
Overview
Main PCA
RS-232 Ports
Micro Floppy Disk System
Hard Disk System
Power Supply
Operator's Display and Keypad
Probe/Pulser, Clock Module, Monitor
Main PCA (MC68000 Microprocessor)
Signal and Pin Description
Programmer's Keyboard
I/O Module
9100A Block Diagram
9105A Block Diagram
68000 Pin Assignments Chart
Signal Descriptions
Signal Organization
Data Strobe Control
Address/Data Bus Operation
Bus Operation During Data Transfer
Address Ranges
The Read Cycle
The Write Cycle
The Read-Modify-Write Cycle
Bus Arbitration
Bus Error and Halt
Privilege Modes
Exception Processing
Interrupts
Interrupt Vector Table
Parity Error Interrupt
Microprocessor Status Latches U61 & U62
Floppy Data Interrupt
DTIO #1 Interrupt
DTIO #2 Interrupt
MFI Card Interrupt 2
Expansion Card Interrupt 2
Floppy Controller Interrupt, Probe Interrupt
I/O Overcurrent Interrupt
Pod Interrupt and Pod Power Fail Interrut
I/O Module General Interrupt
No Interrupt
Asynchronuous Execution
Reset Signal Description and Generation
Address Decoding and DTACK
RAM Configuration
RAM Configuration (U83)
RAM Timing
RAM Refresh
RAM Parity
Rom
ROM Select Logic Table
POD Interface
Pod Control Port Bit Assignment
Pod Interface Pinout
DUART-Timer-I/O
DTIO #1 (Channels A, B) Register Addressing and Description
DTIO #2 (Channels C, D) Register Addressing and Description
Microfloppy Disk System
Disk Drive
Floppy Drive Controller
Floppy Controller Addressing
Floppy Drive Control Latch Outputs
Power Supply Pinout
Operator's Display
Vacuum-Fluorescent Display (VFD)
Vacuum Fluorescent Display
Displayable Characters
Ribbon Cable Connections
Display Characters
Control Characters
Annunciators
Operator's Keypad
Probe I/O Module Interface
Probe I/O Interface Block Diagram
Probe I/O Module Interface Addressing
Probe I/O Module Interface Address Map
Probe Interface
Probe Data Input
Threshold Voltage Calculation
Voltage Threshold Levels
Probe Operation Voltages
Fuse Blown Detection
Probe Light Drive and Control
External 16-Bit Counter
Clock Module Interface
Custom Delay Chip
Functions of U18
Custom Logic Chip
Stop Counter
I/O Module Interface Connector
I/O Module - VDVR Voltage Regulator
VDRV Voltage Regulator Simplified Schematic
I/O Module Overcurrent Detection
Miscellaneous Functional Blocks
Sync Pulse Isolation
Footswitch Connector
Data Bus Buffers
Status Register
Status Register Bit Breakdown
Control Register
I/O Connector Interface
Power Supplies
I/O Module Connector PCA Contents
Probe/Pulser
Probe Tip Input
Probe/Pulser Functional Block Diagram
Probe Speed Specifications
Common Ground Clip
Pulser
Probe Response Timing Specifications
Typical Probe Pulser Amplitude
Pulser Pulse Width
Level Indicators
Logic Level Modes, Level Indicator Operation
Push Button Switch
Clock Module
Multi-Function Interface
Clock Module Operation
Clock Module Speed
Addresses, Clock
Scsi
Video
Video Controller
Video RAM
Video Display Address Mapping
Video Character Data Format
Monitor, Programmer's Keyboard
I/O Module Overview
I/O Module Functional Block Diagram
Bus Interface Functional Block
Addressing
I/O Module Address Decoding Summary
Address Decoding Example
Hot-Bit Decoding Examples
Custom Chip Selection
Bus Interface Timing Diagram
Custom Chip Functional Block
Clock and Enable Mux Functional Block
Clock and Enable Mux Operation
Custom Chip Pin Description
U18 Truth Table
General Control Latch Functional Block
Data Comparison Inputs
Fuse Detection
Data Comparison and General Interrupts
Operation of General Control Latch Block
Threshold Voltage Generation
I/O Module Command Register
VHI and VLO for TTL and CMOS Logic Levels
Custom Chip Voltage Level Detection
Multi-Detection and Interrupt
Fuse Blown Detection Info
Connector Code Functional Block
Dip-Clip and Calibration Module Configuration Codes
Connector Code Examples
Input Protection/Fet Output Block
Input Protection Section Operation
FET Output Section Operation
Chip Channel Input/Pattern Drive Output Simplified Schematic
Logic Levels of NDRV and PDRV Table
I/O Module Top PCA Functional Block
Dip Clip and Calibration Module Functional Block
Overview of the Clip and Calibration Modules
Clup and Calibration Module Operation
Half Width Clip Module
Full-Width Clip Module
Calibration Module
Static Awareness
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Quick Links
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9100A System View
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9100A System Components
3
Calibration Module
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Operating Manual
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Manual
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