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9100A-017
been executed. The COMMON lead should always be connected
to the UUT except during self test and calibration.
On the right side of the Vector Output I/O Module is a 6-pin
connector. These pins perform the following functions:
•
DR CLK
A user-supplied clock that can be selected to drive out the
vectors. This input can be clocked at up to 25 MHz (the
signal must conform to the specifications listed in Section
2). Either a rising or falling edge can be selected as the
clocking edge (using the edgeoutput command). This in-
put can synchronize the vectors with a UUT, synchronize
multiple modules to the same clock, or provide a custom
clock speed for an application.
•
TRISTATE
A user-supplied tri-state input signal. When an active low
signal is present on this input, all 40 outputs of the Vector
Output I/O Module are tri-stated immediately (see the
specifications in Section 2 of this manual for activation
time txout). TRISTATE must go high no later than the re-
covery time txsu after the clocking edge of INT CLK or
DR CLK for the vector to be output. Otherwise, that vec-
tor is only driven internally and the output is held tri-
stated, effectively skipping that vector.
•
WAIT
A user-supplied handshake input signal used in association
with the vector file WAIT command. This pin synchro-
nizes vector output communication between the UUT and
the Vector Output I/O Module. When a WAIT command
occurs in a vector file, no new vectors are driven until the
proper signal edge is received on this input. The WAIT
command in the vector file determines which edge of the
signal on this pin is considered valid (see Section 6 of this
manual for more information on the vector editor WAIT
command).
4-2
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