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•
CE (which is controlled by PS7) has a setup time of 0 ns
prior to RD going low.
•
RD has a minimum pulse width of 200 ns.
•
Data D7 through D0 will be valid a maximum of 100 ns
after RD goes low.
•
Address bus A11 through A1 and CE have a 0 ns hold time
after RD goes high.
•
CE must be high for 300 ns between chip accesses.
The following 2674 Video Display Controller Read Cycle vector
file performs a read cycle.
2674 Video Display Controller Read Cycle
GROUPS [40-30,1][29-22][21-14][13][12][11][10][9][8][7][6][5-2]
DISPLAY HEX,HEX,HEX,BIN
!
ADDR
!
A11 - A1
D15-D8
!
!
!
!
!
!
! READ CYCLE addr $f0011 (addr $fxxxx =PS7-, data = LDS-)
1 $011
2 $011
WAIT -
3 $003
CAPTURE
STOP
The first vector in this file sets the address. Vector 2, which is
driven 200 ns later holds the address holds R/W high and sets
LDS low (to get RD low), and sets PS7 low (to get CE low). The
WAIT statement ensures that VDTACK is returned before
continuing. The final vector, which is driven 200 ns later, holds
the address while the CTRL signals are changed to return RD
and CE high. Approximately 100 ns after RD and CE have
returned high (in the center of the vector period), the CAPTURE
clock clocks the data in on the data bus. A readword command
using the "stored" mode can then be performed to retrieve the
data. Note that the read data is only valid for 100 ns maximum
after the return of RD and CE to the high state. If the read
DATA
D7-D0
$XX
$XX
$XX
$XX
$XX
$XX
CTRL
R
U
L
P
P
R
V
/
D
D
S
S
E
W
W
S
S
7
6
S
A
-
-
-
-
-
E
I
T
T
-
-
1
1
1
1
1
1
X
1
1
0
0
1
1
X
1
1
1
1
1
1
X
9100A-017
UNUSED
V
D
T
A
C
K
-
X
XXXX
X
XXXX
X
XXXX
7-17
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