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A logic analyzer may also be useful for determining cycle infor-
mation. The logic analyzer can be connected to a known-good
system with the UUT plugged into a motherboard so the cycles
can be observed. The analyzer can also provide other informa-
tion (such as initialization sequences, handshaking protocols,
etc.) that may be necessary to perform bus communication.
There are two methods by which a read cycle may be imple-
mented:
•
For read cycles where individual data reads are not impor-
tant or not possible (such as block reads), but the block of
data must be correct, a cyclic redundancy check (CRC) can
be used to verify the data. When CRC checking is used,
read cycles occur at full speed with no delays between cy-
cles.
•
For read cycles where the individual data must be ob-
served, a TL/1 readword function must be performed after
each cycle. By using the "capture" sync mode and placing
the CAPTURE keyword in the appropriate vector in the
vector file, or by using the "ext" sync mode and connect-
ing the external clock line (CLOCK) to an address strobe or
data strobe, the readword function can read the "stored"
synchronous level history. This method allows read cy-
cles at full speed with some delay between read accesses.
Data Compare Equal (DCE) can trap asynchronous events on the
bus, or can detect bus errors or interrupts if a line(s) of the
Vector Output I/O Module is dedicated for monitoring the event.
For applications where the Vector Output I/O Module provides a
clock to the UUT for synchronization and the skew between INT
CLK and the data out is too large, the vector data output can be
synchronized with the clock by dedicating an output pin of the
module to be the UUT clock.
9100A-017
7-3
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