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9100A-017
Capture Mode
4.16.
The capture sync mode synchronizes the response gathering
hardware with the vector output automatically. When the vector
files are edited, vectors can be programmed to clock the input
section on a single vector, specific vectors, or all vectors. For
more information, refer to Section 6 of this manual for the cap-
ture command description.
After a vector that has been programmed to capture is driven, the
receive hardware is clocked (see Figure 4-5). When syncoutput
mode is "intfreq" or "drclk", the receive hardware is clocked at
about the midpoint of a single vector period (for example, when
a 1 MHz clock is used, a vector period is 1000 ns and clocking
occurs 500 ns after the vector is driven). (For "drclk", a 50%
clock duty cycle is assumed.)
Figure 4-5. Capture Clock Timing Diagram
For all syncoutput modes, capture clock performs without any
user consideration. When the syncoutput mode is "drclk", the
clock cycle should be close to a 50% duty cycle to get receive
clocking in the center of the driven vector. A 50% duty cycle
4-15
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