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high for two cycles (334 ns) to ensure that the data held on the
bus is valid. Using the TL/1 readword command in the "stored"
mode will return the data read.
GROUPS [40-21][20-13][1][2][3][4][5][7][8][6][12-9]
DISPLAY HEX,HEX,BIN
!
A19 - A0
!
!
!
!
!
! START OF READ CYCLE read addr $3D5
1 $003D5
2 $003D5
3 $003D5
4 $003D5
5 $003D5
CAPTURE
6 $003D5
STOP
VIDEO RAM BUS CYCLES
Another pair of bus cycles must be determined for accessing the
video RAM. The access time of the RAM is much greater than
that of the CRT Controller and, because the RAM is shared
between the controller and bus accesses, the IORDY line is used
with the WAIT line of the module to provide synchronization.
In the Video RAM Write Cycle Vector File that follows, vector 1
sets addresses A19 through A0 and data D7 through D0. Vector
2 holds the address and data while MEMW goes low. Upon
receipt of MEMW and the correct address, IORDY goes low.
The module then waits until the UUT acknowledges the write by
returning the IORDY line high, which satisfies the WAIT
condition, and vector driving continues. Vector 3 maintains the
address and data for hold time.
GROUPS [40-21][20-13][1}[2][3][4][5J[7][8][6][12-9]
DISPLAY HEX,HEX,BIN
!
A19 - A0
!
!
!
!
!
! WRITE CYCLE address $B8000, data $41
1 $B8000
CRT Controller Read Cycle Vector File
D7-D0
$XX
$XX
$XX
$XX
$XX
$XX
Video RAM Write Cycle Vector File
D7-D0
$41
I
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M
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9100A-017
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7.8.
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7-9
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