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Fluke 9100 Series Service Manual

Fluke 9100 Series Service Manual

Vector output i/o module
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9100 Series
9100A-017
Vector Output I/O Module
Service Manual
P/N 855531
August 1989
© 1989, John Fluke Mfg. Co., Inc. All rights reserved. Litho in U.S.A.

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  • Page 1 9100 Series 9100A-017 Vector Output I/O Module Service Manual P/N 855531 August 1989 © 1989, John Fluke Mfg. Co., Inc. All rights reserved. Litho in U.S.A.
  • Page 2 To obtain warranty service, contact a Fluke Service Center or send the product, with the description of the difficulty, postage prepaid, to the nearest Fluke Service Center. Fluke assumes no risk for damage in transit.

  • Page 3: Table Of Contents

    Table of Contents ______________________________________________________________________________ SECTION TITLE PAGE Introduction and Specifications ......1-1 INTRODUCTION1 ..........1-1 SPECIFICATIONS ........... 1-1 Theory of Operation ........2-1 VECTOR OUTPUT I/O MODULE OVERVIEW ......2-1 INPUT SECTION THEORY OF OPERATION ......2-5 Mainframe to Bus Interface Functional Block ..2-5 MAINFRAME ADDRESSING OF THE MODULE .....
  • Page 4 SECTION TITLE PAGE Maintenance ..........3-1 INTRODUCTION ..........3-1 CHANGING THE VECTOR OUTPUT I/O MODULE FUSE ....3-1 CLEANING ..........3-2 VECTOR OUTPUT I/O MODULE SELF TEST ....... 3-2 DISASSEMBLY ..........3-2 TROUBLESHOOTING .......... 3-3 General Information ......... 3-3 List of Replaceable Parts ......... 4-1 INTRODUCTION ..........
  • Page 5 List of Tables ______________________________________________________________________________ TABLE TITLE PAGE 1-1. Vector Output I/O Module Specifications ....1-1 2-1. Custom Chip Pin Description ....... 2-11 2-2. Clock and Enable Mux Truth Table ......2-12 2-3. VHI and VLO for TTL and CMOS Logic Levels ....2-15 2-4.
  • Page 6 -iv-...
  • Page 7 List of Figures ______________________________________________________________________________ FIGURE TITLE PAGE 2-1. Input Section Functional Block Diagram ....2-3 2-2. Output Section Functional Block Diagram ....2-4 2-3. Input Section Address Decoding Summary ....2-7 2-4. Address Decoding Example ........2-8 2-5. Hot-Bit Decoding Examples ......... 2-9 2-6.
  • Page 8 -vi-...

  • Page 9: Introduction And Specifications

    Section 1 Introduction and Specifications INTRODUCTION This manual presents service information for the 9100A-017 Vector Output I/O Module. Included are a theory of operation, general maintenance procedures, performance tests, troubleshooting information, a list of replacement parts, and schematic diagrams. SPECIFICATIONS Table 1-1 contains the specifications for the Vector Output I/O Module.
  • Page 10 ENABLE Hold Time ....20 ns minimum. ______________________________________________________________________________ Skew measurement assumes equal loading. Differences in capacitance may affect results. Capture clock may be adjusted in approximate 15 ns steps by using the setoffset command (see the 9100 Series TL/1 Reference Manual). ______________________________________________________________________________...
  • Page 11 1/Introduction and Specifications Table 1-1. Vector Output I/O Module Specifications (cont.) ______________________________________________________________________________ DR CLK START Setup Time ....20 ns minimum. STOP Setup Time ....20 ns minimum. ENABLE Setup Time ....15 ns minimum. ENABLE Hold Time ....35 ns minimum. Input Impedance: DR CLK .........
  • Page 12 1/Introduction and Specifications Table 1-1. Vector Output I/O Module Specifications (cont.) ______________________________________________________________________________ Transition Counter: Maximum Frequency ...... 10 MHz minimum. Maximum Count (Transition Mode) ..8388608 (23 bits) counts (+ overflow). Frequency Accuracy (Frequency Mode) ..±250 ppm ±2 Hz. Stop Counter: Maximum Frequency ......

  • Page 13: Theory Of Operation

    Section 2 Theory of Operation VECTOR OUTPUT I/O MODULE OVERVIEW The 9100A-017 Vector Output I/O Module adds 40 lines of input and high-speed output capability to the 9100A/9105A mainframe. Up to four Vector Output I/O Modules may be connected to the mainframe for a maximum of 160 channels of vector output and stimulus measurement.
  • Page 14 2/Theory of Operation vector drive status register. six-pin jack for control signals for vector driving. The Top PCA is used primarily for vector output, although it also provides the 40-channel input signals, Clip Module Connector Code, and ready button signals to the input section on the Main PCA. It also generates the Capture Clock (available as an input sync mode).

  • Page 15: Input Section Functional Block Diagram

    2/Theory of Operation Figure 2-1. Input Section Functional Block Diagram...

  • Page 16: Output Section Functional Block Diagram

    2/Theory of Operation Figure 2-2. Output Section Functional Block Diagram...

  • Page 17: Input Section Theory Of Operation

    2/Theory of Operation INPUT SECTION THEORY OF OPERATION NOTE All of the input section circuitry is located on the Main PCA unless otherwise indicated. Mainframe to Bus Interface Functional Block The bus interface block connects the 9100A/9105A mainframe microprocessor bus to the Vector Output I/O Module. The module is a memory-mapped device, with all control performed by writing to the module memory space.

  • Page 18: Custom Chip Selection

    2/Theory of Operation shows the third least significant digit of the 5-digit hex module address broken down into binary format. The position of the set bit(s) determines the module(s) to be addressed. The Vector Output I/O Module bus interface timing diagram (Figure 2-6) shows the signals contained in the bus interface block during a read and write cycle.

  • Page 19: Input Section Address Decoding Summary

    2/Theory of Operation Figure 2-3. Input Section Address Decoding Summary...

  • Page 20: Custom Chip Functional Block

    2/Theory of Operation Figure 2-4. Address Decoding Example low. U6 decodes the latched address lines and sets output line AD8- low. The logic low on AD8- is gated through U5 and sets up a logic low on CS0-, thereby enabling custom chip U100. To select custom chip U100 on Module 3, the address $D0481 is used.

  • Page 21: Clock And Enable Mux Functional Block

    2/Theory of Operation Figure 2-5. Hot-Bit Decoding Examples connected to the data bus via U8. Eleven internal registers control each custom chip. These registers are in turn controlled by address lines A1 through A3 and the R/W- line. The pin-out of the custom chip is shown in Table 2-1. Clock and Enable Mux Functional Block The Clock and Enable Mux block is located on the Main PCA and is shown in the Input Section Functional Block Diagram, Figure 2-1.

  • Page 22: Bus Interface Timing Diagram

    2/Theory of Operation Figure 2-6. Bus Interface Timing Diagram The Clock and Enable Mux block enable sources include BUFENABLE, a signal that originates from the external ENABLE synchronization line, and PSYN (described in the previous paragraph). The CALCLK2 signal enters the Main PCA through the Connector Code block.

  • Page 23: General Control Latch Functional Block

    2/Theory of Operation Table 2-1. Custom Chip Pin Description ______________________________________________________________________________ TYPE FUNCTION ______________________________________________________________________________ A0-A2 Input Address Lines POR- Input Power-On Reset SRCK Input 1 MHz Serial-To-Parallel Conversion Clock VDD1 Input Positive Voltage Supply VDD2 Input Positive Voltage Supply GND1 Input Logic Common GND2 Input...

  • Page 24: Control Register

    2/Theory of Operation Table 2-2. Clock and Enable Mux Truth Table ________________________________________________________ Control In Outputs ________________________________________________________ CLKMUX ENAMUX ________________________________________________________ BUFENABLE BUFCLOCK PSYN BUFCLOCK BUFENABLE CAPTURE- PSYN CALCLK2 ________________________________________________________ block diagram. The ICs in this block include: a 74HC273 8-Bit Latch (U14), an LM324 Quad Op-Amp (U2), two 2N3906 PNP transistors (Ql, Q2), a 74HC08 Quad 2-Input AND Gate (U3), a 74LS30 8-Input NAND Gate (U15), two 74LS112 Dual JK Negative-Edge-Triggered Flip-Flops (U11, U12), a 74HCT32...

  • Page 25: Data Comparison And General Interrupts

    2/Theory of Operation the module Main PCA protects the ground line. The FUSEDET signal becomes an input to the interrupt register (U13-8), along with the other detection signals. DATA COMPARISON AND GENERAL INTERRUPTS The General Control Latch block outputs detection and interrupt signals for any problems or special operations of the module.

  • Page 26: I/O Module Control And Interrupt Registers

    2/Theory of Operation Threshold Voltage Generation Threshold Voltage Generation produces the threshold voltages necessary for the custom chips to classify input logic levels. Data bit 7 of the command register (U14) determines the level of the threshold, with a 1 selecting TTL, and a 0 for CMOS.

  • Page 27: Custom Chip Voltage Level Detection

    2/Theory of Operation together provide a regulated output with high current sinking capability. Typical current seen by these regulators can vary from 10 to 40 mA. The approximate VHI and VLO levels generated are listed in Table 2-3. Table 2-3. VHI and VLO for TTL and CMOS Logic Levels _____________________________________________________________ DESC...

  • Page 28: Connector Code Functional Block

    2/Theory of Operation the full-size module plugs into both connectors (both J1 and J2 on the Top PCA). Together, the clip(s) plugged into both J1 and J2 of the Top PCA generate an 8-bit code that can be decoded by the mainframe to identify the size of the installed clip module(s).

  • Page 29: Main Pca To Top Pca Interface Functional Block

    2/Theory of Operation Table 2-4. Dip-Clip and Calibration Module Configuration Codes ______________________________________________________________________________ 4-BIT CODE MEANING ______________________________________________________________________________ 0000 14-Pin Clip 0001 16-Pin Clip 0010 18-Pin Clip 0011 20-Pin Clip 0100 24-Pin Clip 0101 (reserved) 0110 Used as most significant byte of calibration header 0111 (reserved) 1000...

  • Page 30: Addressing

    2/Theory of Operation Table 2-5. Connector Code Examples _________________________________________________________________ CODE READ MEANING _________________________________________________________________ No clip on B side, 20-pin clip on A side 24-pin clip on B side, no clip on A side 40-pin clip installed 16-pin clip on B side, 24-pin clip on A side No clips installed ________________________________________________________________ qualified RD- and WR- are also available to the output section.
  • Page 31 2/Theory of Operation Table 2-6. Vector I/O Module Output Section Address Map ______________________________________________________________________________ ADDRESS WRITE READ ______________________________________________________________________________ $DOX01 COMMAND0- Vector Drive Status Nybble $DOX11 COMMAND1- ---- $DOX21 Drive Register 2 (U25) ---- $DOX31 Loop Counter Load ---- (LCLO- or LCHI-) $DOX41 RAM-PORT- RAM-PORT-...

  • Page 32: Internal Oscillator Control Functional Block

    2/Theory of Operation Internal Oscillator Control Functional Block The Vector Output I/O Module contains a 1, 5, 10, and 20MHz internal clock source that is available for vector driving. The desired clock can be selected by writing to Drive Register 2 (U25) of the Main PCA ($DOX21) and specifying bits 1 and 0.

  • Page 33: Ram Select Functional Block

    2/Theory of Operation the LOAD-RAM-HI- and LOAD-RAM-LO- signals that control the Vector RAM Address Functional Block. For more information on the available addresses and the signals they affect, see Table 2-6. Table 2-8 illustrates the U5 register bits used by the Output Control Functional Block.

  • Page 34: Chip Counter Operation

    2/Theory of Operation module output to an unchanging state. There are two methods by which the Vector Pattern RAM and the Vector Control RAM can be selected: To drive vectors, the DRV/LD- signal must be set high by performing a write to the U5 register 0 ($D0X01) with bit 3 set high. This causes all outputs of U11 (BYTE0- through BYTE9-) and the BYTE10- output of U10 to be low, thereby selecting all vector RAM.

  • Page 35: Drive Clock Selection

    2/Theory of Operation determines if the vector drive clock should be always enabled or if the external ENABLE should be used. Bit 2 determines if the vector output should be “force” started (no external start required) or if the external START is required. Bit 1 determines if the external STOP signal should terminate vector driving or not.

  • Page 36: Handshake Synchronization

    2/Theory of Operation SSGATE- on U12 pin 6 provides the qualifying signal to the clock. In order to have the clock qualified, the following conditions must be met: U12 pin 1 must be high. This line insures that a start has been received, either by the FOR-START- line being low or by the STRP signal having the programmed edge on the external START line.

  • Page 37: Vector Drive Complete Logic

    2/Theory of Operation VECTOR DRIVE COMPLETE LOGIC There are two different mechanisms for controlling the completion of vector driving, both of which are selected by the vector file in use. The Vector Drive Complete circuitry consists of a 74AC02 NOR Gate (U20), a 74ACT86 Exclusive OR Gate (U17), a 74ACT74 D Flip-flop (U16), and a 74AC08 AND Gate (U19).

  • Page 38: Vector Address Functional Block

    2/Theory of Operation Vector Address Functional Block The Vector RAM Address Registers U1 and U2 are loaded by the following procedure: The least significant byte (LSB) and the most significant byte (MSB) of the address are loaded into U4 and U3 by performing writes to $D0X71 and $D0X61 respectively, and then writing $D0X01 with bit 7 low and then high, toggling the LOAD-RAM- signal and parallel loading the address.

  • Page 39: Loop Control Functional Block

    2/Theory of Operation The Vector Control RAM Functional Block consists of an 8K x 8 SRAM (U600), a 74AC273 Octal D-Type Flip-Flop (U601), a resistor pack (Z600), and one 74AC08 AND gate (U19). The Z600 resistor pack provides isolation from the D-BUS data bus. When only U600 has been selected to be written to, the data on the bus passes through Z600 and is input to U600.

  • Page 40: Capture Clock Functional Block

    2/Theory of Operation step is repeated for the other byte (either the MSB or the LSB). Finally, another write is made to $D0X21 with bit 2 set that releases the clear on U28. When a vector file is driven, on the vector prior to the one designated by the ENDLOOP statement on the vector file the LOOP output (U601-5) goes high.

  • Page 41: Output Protection Functional Block

    2/Theory of Operation Table 2-10. U25 ID/Status Register Bit Description (Read @ $D0X01) ___________________________________________________________________________ SIGNAL ___________________________________________________________________________ DONE Not Done Done HS-ENABLE Not Suspended Suspended ID CODE = 01 ___________________________________________________________________________ Output Protection Functional Block The vector data on the OUT-BUS of the Top PCA is connected to diode packs (BAV99) that are connected to +5 volts and ground to clamp overvoltage and undervoltage on the outputs.
  • Page 42 2/Theory of Operation 2-30...
  • Page 43 3. Using the procedures, and packaging and bench techniques that are recommended. The Static Sensitive (S.S.) devices are identified in the Fluke technical manual parts list with the symbol The following practices should be followed to minimize damage to S.S. devices.
  • Page 44 SUCKERS SHOULD BE USED. 11. ONLY GROUNDED TIP SOLDERING IRONS SHOULD BE USED. A complete line of static shielding bags and acces- sories is available from Fluke Parts Department, Telephone 800-526-4731 or write to: JOHN FLUKE MFG. CO., INC. ®...

  • Page 45: Maintenance

    Section 3 Maintenance WARNING SERVICING DESCRIBED IN THIS SECTION IS TO BE PERFORMED BY QUALIFIED SERVICE PERSONNEL ONLY. TO AVOID ELECTRICAL SHOCK, DO NOT PERFORM ANY SERVICING UNLESS YOU ARE QUALIFIED TO DO SO. INTRODUCTION This section describes maintenance procedures for the 9100A-017 Vector Output I/O Module.

  • Page 46: Cleaning

    3/Maintenance CLEANING CAUTION Do not use aromatic hydrocarbons (such as gasoline or other fuels) or chlorinated solvents for cleaning. They may damage plastic materials used in the instrument. Do not use detergent of any kind for cleaning the PCA. Clean the instrument case with a mild detergent and water. The main and top PCAs may be washed with isopropyl alcohol or deionized water and a soft brush.

  • Page 47: Troubleshooting

    Vector Output I/O Module PCAs. For more complete information on testing and troubleshooting, along with software to supplement the tests, a 9100A Service Kit (John Fluke Part Number 818948) can be purchased. General Information If the Vector Output I/O Module fails the self test, the PCA that failed can usually be quickly isolated.
  • Page 48 3/Maintenance U502 on the Top PCA) has four channels of output. By observing the failure mask and using the single-point probe for verification, the faulty PCA (Top or Main) can be isolated.

  • Page 49: List Of Replaceable Parts

    Section 4 List of Replaceable Parts ____________________________________________________________________________ TABLE OF CONTENTS TABLE FIGURE ASSEMBLY NAME DRAWING NO. PAGE PAGE 9100A-017 Final Assembly 9100A-017 A1 Main PCA 9100A-4021 A2 Top PCA 9100A-4022 4-10 4-11...
  • Page 50 4/List of Replaceable Parts...

  • Page 51: Introduction

    Components may be ordered directly from the manufacturer’s part number, or from the John Fluke Manufacturing Co., Inc., or an authorized representative by using the Fluke Stock Number. In the event the part ordered has been replaced by an new or improved part, the replacement will be accompanied by an explanatory note and installation instructions if necessary.

  • Page 52: Additional Information

    4/List of Replaceable Parts ADDITIONAL INFORMATION Table 4-4 lists the revision levels of the PCAs documented in this manual. To identify the configuration of the PCAs used in your instrument, refer to the revision letter on the component side of each PCA.
  • Page 53 4/List of Replaceable Parts Table 4-1. 9100A-017 Vector I/O Final Assembly (See Figure 4-1.) REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK PART NUMBER -A>-NUMERICS----> S--------------DESCRIPTION-------------- --NO-- -CODE- -OR GENERIC TYPE----- QTY- -E- * MAIN PCA 846329 89536 846329 * TOP PCA...

  • Page 54: 9100A-017 Final Assembly

    4/List of Replaceable Parts Figure 4-1. 9100A-017 Final Assembly...
  • Page 55 4/List of Replaceable Parts Figure 4-1. 9100A-017 Final Assembly (cont.)
  • Page 56 4/List of Replaceable Parts Table 4-2. A1 Main PCA (See Figure 4-2.) REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER -A>-NUMERICS----> S--------------DESCRIPTION-------------- --NO-- -CODE- -OR GENERIC TYPE----- QTY- -E- CAP,TA,10UF,+-20%,25V 772491 56289 195D106X0025X2T 10, 17, 18, 772491 27, 37, 42-...
  • Page 57 4/List of Replaceable Parts Figure 4-2. A1 Main PCA...
  • Page 58 4/List of Replaceable Parts Table 4-3. A2 Top PCA (See Figure 4-3.) REFERENCE FLUKE MFRS MANUFACTURERS DESIGNATOR STOCK SPLY PART NUMBER -A>-NUMERICS----> S--------------DESCRIPTION-------------- --NO-- -CODE- -OR GENERIC TYPE----- QTY- -E- 5, 46, CAP,TA,10UF,+-20%,25V 772491 56289 195D106X0025X2T 772491 6- 45, 48, CAP,CER,0.1UF,+-10%,25V,X7R,1206...
  • Page 59 4/List of Replaceable Parts Figure 4-3. A2 Top PCA 4-11...
  • Page 60 4/List of Replaceable Parts Table 4-4. Module Revision Information ______________________________________________________________________________ Ref. Assembly Fluke Revision Name Part No. Level ______________________________________________________________________________ Main PCA 873948 Top PCA 873950 ______________________________________________________________________________ 4-12...
  • Page 61 4/List of Replaceable Parts MANUFACTURER’S FEDERAL SUPPLY CODES 00779 25403 56289 75569 AMP, Inc. Amperex Electronics Corp. Sprague Electric Co. Performance Semiconductor Corp. Harrisburg, Pennsylvania Semiconductor & Micro-Circuit Div. North Adams, Massachusetts Sunnyvale, California Slatersville, Rhode Island 01295 59124 9W423 Texas Instruments Inc.
  • Page 62 5640 Fishers Lane Tel: 416-890-7600 Germany (F.R.G.) Rockville, MD 20852 Philips GmbH Japan Tel: (301) 770-1576 Chile Service fuer FLUKE - Produkte John Fluke Mfg. Co., Inc. Intronsa Inc. Department VSF Japan Branch New Jersey Casilla 16158 Oskar-Messter-Strasse 18 Sumitomo Higashi Shinbashi Bldg.
  • Page 63 4/List of Replaceable Parts TECHNICAL SERVICE CENTERS New Zealand Singapore Thailand Philips Customer Support Rank O’Connor’s Singapore Pte Ltd Measuretronix Ltd. Scientific & Industrial Division 98 Pasir Panjang Road 2102/63 Ramkamhaeng Rd. 2 Wagener Place Singapore 0511 Bangkok 10240 Mt. Albert Tel: 65 4737944 Tel: 66 2 374-2516, 374-1632 Auckland...
  • Page 64 4/List of Replaceable Parts 4-16...

  • Page 65: Schematic Diagrams

    Section 5 Schematic Diagrams ______________________________________________________________________________ CONTENTS FIGURE TITLE PAGE 5-1. A1 Main PCA ..........5-3 5-2. A2 Top PCA ..........5-5...
  • Page 66 5/Schematic Diagrams...

  • Page 67: A1 Main Pca

    5/Schematic Diagrams Figure 5-1. A1 Main PCA...
  • Page 68 5/Schematic Diagrams Figure 5-1. A1 Main PCA (cont.)

  • Page 69: A2 Top Pca

    5/Schematic Diagrams Figure 5-2. A2 Top PCA...
  • Page 70 5/Schematic Diagrams Figure 5-2. A2 Top PCA (cont.)
  • Page 71 Index ______________________________________________________________________________ Address Map, Output Section, 2-19 Addressing, Mainframe Addressing of the Module, 2-5 Output Section, 2-18 Calibration Module, 2-10, 2-17 CAPTURE, 2-9 Capture Clock Functional Block, 2-28 Chip Counter Operation, 2-22 Cleaning the Module, 3-2 Clip Module, 2-16 Clock and Enable Mux Functional Block, 2-9 Connector Code Functional Block, 2-16 Control Register, 2-12 Custom Chip Selection, 2-6...
  • Page 72 Index Functional Blocks, SSLOGIC (Start/Stop Logic), 2-22 Vector Address, 2-26 Vector Control RAM, 2-26 Vector Pattern RAM, 2-26 Fuse Blown Detection, 2-16 Fuse, Changing, 3-1 Fuse Detection, 2-12 General Control Latch Functional Block, 2-11 General Interrupts, 2-13 General Stop, Performing, 2-25 Handshake Synchronization, 2-24 I/O General Interrupt, 2-13 Input Protection Functional Block, 2-16...
  • Page 73 Index STROBE-, 2-5 Suspending Vector Driving, 2-24 Threshold Voltage Generation, 2-14 TRISTATE-, 2-26 Troubleshooting the Module, 3-3 Vector Address Functional Block, 2-26 Vector Control RAM, 2-22, 2-26 Vector Drive Complete Logic, 2-25 Vector Drive Status Nybble, 2-18, 2-24 Vector Drive Termination, 2-27 Vector Output I/O Module Overview, 2-1 Vector Pattern RAM, 2-22, 2-26 Vector RAM Address Register, 2-23...
  • Page 74 Index Index-4...

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