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9100A-017
Table 2-1. Vector Output I/O Module Specifications (cont)
Clock to Vector Out (tdel):
INT CLK Out to Vector Out Delay .....................37 ns typical, 45 ns maximum.
DR CLK in to Vector Out Delay.........................50 ns typical, 58 ns maximum.
WAIT (Handshake) Setup Time (twsu) ..................42.5 ns maximum (35 ns typical)
Single Module Channel to Channel Skew * ...........6 ns Maximum (1 ns typical).
Module to Module Channel Skew *........................10 ns Maximum (1 ns typical).
TRISTATE:
Activation (txout) ...............................................Output source/sink released 25 ns
Recovery (txsu)................................................. TRISTATE must go high no later
Output Series Termination .....................................33 Ohms
Capture Clock: **
INT CLK ............................................................Capture Clock clocks 42.5 ns ±5 ns
DR CLK.............................................................Capture Clock clocks 55 ns ±10 ns
START, STOP, and ENABLE:
START, STOP pulse width .....................................10 ns minimum
INT CLK
START Setup Time ......................................30 ns minimum
STOP Setup Time ........................................30 ns minimum
ENABLE Setup Time....................................25 ns minimum
ENABLE Hold Time......................................20 ns minimum
DR CLK
START Setup Time ......................................20 ns minimum
STOP Setup Time ........................................20 ns minimum
ENABLE Setup Time....................................15 ns minimum
ENABLE Hold Time......................................35 ns minimum
Input Impedance:
DR CLK.............................................................40 KQ minimum, 35 pF maximum.
TRISTATE .........................................................40 KQ minimum, 80 pF maximum.
WAIT .................................................................40 KQ minimum, 50 pF maximum.
*
Skew measurement assumes equal loading. Differences in capacitance may affect
results.
**
Capture clock may be adjusted in approximate 15 ns steps by using the setoffset
command (see the 9100 Series TL/1 Reference Manual).
2-2
from WAIT acknowledgement until
next dock cycle drives vector. If the
setup time is not met, the next clock
drives out the vector. Minimum
WAIT pulse width is 10 ns.
maximum (20 ns typical) after
TRISTATE goes low. Minimum
TRISTATE pulse width is 10 ns.
than 5 ns after the rising edge of
the INT CLK or no later than 10 ns
after the clocked edge of DR CLK
for the vector to be output by that
dock, otherwise that vector is only
driven internally and the output is
held tri-stated, effectively skipping
that vector.
after the falling edge of INT CLK.
after non-clocking edge of DR CLK
(approximate 50% duty cycle).
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