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MC6845 CRT CONTROLLER BUS CYCLES
Examine the timing diagram for the MC6845 (shown in Figure
7-1) to determine the vector patterns necessary to achieve the
required bus cycles.
To perform a read/write cycle, the following conditions must be
met:
•
The address (RS) and read/write (R/W) signal must be set a
minimum of 80 ns before the rising edge of the E clock and
held for 10 ns after the falling edge of the clock.
•
WRITE DATA must be set a minimum of 165 ns before the
falling edge of the E clock and held for 10 ns after the fall-
ing edge of the clock.
•
READ DATA must be output a maximum of 290 ns after
the rising edge of the E clock and will be held for a maxi-
mum of 50 ns after the falling edge of the E clock.
The following CRT Controller Write Cycle Vector File contains
the vectors necessary to perform the write cycle. Since the
driven vectors are synchronized with the 6 MHz bus clock, each
Figure 7-1. MC6845 Cycle Timing Diagram
9100A-017
7.7.
7-7
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