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Figure 7-2. SCN2674 Controller Timing Diagram (4 MHz Version)
•
CE (which is controlled by PS7) has a setup time of 0 ns
prior to R/W going low.
•
WR has a minimum pulse width of 200 ns.
•
Data D7 through D0 must be setup 150 ns minimum before
WR goes high.
•
Data D7 through D0 must be held a minimum of 5 ns after
WR goes high.
•
Address bus A11 through A1 and CE have a 0 ns hold time
after WR goes high.
•
CE must be high for 300 ns between chip accesses.
Using an internal clock frequency of 5 MHz (which gives 200 ns
per vector resolution), the following 2674 Video Display
Controller Write Cycle vector file can be made.
9100A-017
7-15
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