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9100A-017
The enabling condition need not always depend on
the specified state (HIGH, LOW, ALWAYS) of the
Enable input. The enabling condition can also
involve the state of the internal PodSync line.
After an ARM I/O MOD command is entered and after a valid
Start edge is detected, the measurement period begins. Start is
recognized independently of the enabling condition, but data is
only gathered after the enabling condition becomes true.
Synchronous data is gathered after the same point, but only at
the selected clock edges.
The data gathering period ends when the Stop condition be-
comes true: the selected Stop edge occurs, or a programmed
number of clock edges completes. After the period ends, enter
the appropriate SHOW I/O MOD command (found under the
Mainframe I/O MOD key), which displays data gathered by the
following:
•
CRC signature register.
Contains signature data clocked in at each enabled clock
edge between Start and Stop.
•
Clocked level history register.
Contains all logic levels (1, 0, X) seen at each enabled
clock edge between Start and Stop.
•
Asynchronous level history register.
Contains all logic levels (1, 0, X) seen while enabled be-
tween Start and Stop. An X level must be present for a
fixed period before being recorded because an X should not
be recorded during fast 0-to-1 or 1-to-0 transitions, which
do pass briefly through the invalid (X) region.
4-12
NOTE
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