Table of Contents
Advertisement
9100A-017
CTS, 7-18
Cyclic redundancy check, 7-3
Data Compare Equal, 7-3
Data fields, 6-6
DCE, 4-3
Determining bus cycles, 7-14
Determining the read cycle, 7-16
Determining the write cycle, 7-14
Display line, 6-5
DR CLK, 4-2, 4-16
drivepoll, 5-1, Appendix A
edgeoutput, 5-2, Appendix A
ENABLE, 4-1
enableoutput, 5-3, Appendix A
Endloop, 6-11
External, I/O Module to, 4-7
External lines, 4-10
External sync mode, 4-11
Fixture, 4-10, 7-5, 7-13
Flying lead set, 4-10
Freerun sync mode, 4-14
Fuse, 4-3
Groups line, 6-4
Handshake input, 4-2
Handshake status, Appendix A
Handshaking, 3-2
I/O Module to external, 4-7
I/O Module clip/pin mapping, Appendix B
I/O Module to pod, 4-8
INT CLK, 4-3, 4-16, 7-3
Internal clock delay, 4-7
Internal sync mode, 4-14
Keypad reference changes, Appendix C
Loop, 6-11, 7-19
Loop control, 3-2
MC6845 bus cycles, 7-7
INDEX-2
Advertisement
Table of Contents
