Page 2 Fluke Service Center. Fluke assumes no risk for damage in transit. Fluke will, at our option, repair or replace the defective product free of charge. However, if we determine that the failure was caused by misuse, alteration, or abnormal condition of operation or handling, you will be billed for the repair.
Page 3: Table Of Contents
Contents Section Title Page Introduction ...................1-1 1-1. THE VECTOR OUTPUT I/O MODULE ......1-1 1-2. HIGH SPEED PARALLEL STIMULUS .......1-1 1-3. BUS EMULATION ..............1-2 1-4. TEST VECTOR PATTERN GENERATION ......1-2 1-5. USER OPERATIONS ............1-3 Specifications ................2-1 2-1. SPECIFICATIONS ..............2-1 Vector Output Operation ..............3-1 3-1.
Page 4: Section Title Page
Section Title Page 4-7. CONNECTING THE MODULE TO THE UUT ..............4-9 4-8. Using the Clip Modules ..........4-9 4-9. Connecting the External Lines ........4-10 4-10. Using the Card Edge Fixture Kit ........4-10 4-11. SYNCHRONIZING THE MODULE TO THE UUT ....4-11 4-12.
Page 5 Section Title Page 7-3. TESTING THE IBM CGA VIDEO CARD ......7-4 7-4. Fixturing the CGA Interface ...........7-5 7-5. Fixturing Considerations ..........7-6 Vector File Programming ..........7-6 7-9. Vector File Generation ...........7-10 7-10. CGA Write/Read Program Example ......7-11 7-11. 68000 BUS VIDEO APPLICATION ........7-12 7-12.
Page 7 Tables Table Title Page 2-1. Vector Output I/O Module Specifications ......2-1 7-1. CGA to Vector Output I/O Module Mapping .......7-5 7-2. Video Board to Vector Output I/O Module Mapping ...7-13...
Page 8 viii...
Page 9 Figures Figure Title Page 3-1. WAIT Input Timing Diagram ..........3-3 3-2. TRISTATE Input Timing Diagram ........3-4 4-1. Vector Output I/O Module Block Diagram ......4-4 4-2. Vector Output I/O Module Output Section ......4-4 4-3. Input Section Block Diagram ..........4-5 4-4. Pod Sync Input/Output Section Timing Diagram ....4-13 4-5.
Page 11: Introduction
Introduction THE VECTOR OUTPUT I/O MODULE 1.1. The Fluke 9100A-017 Vector Output I/O Module adds high speed test stimulus capabilities to the 9100A Digital Test System and 9105A Digital Test Station (referred to in this manual as the Mainframe). The 9100A-017 can generate vectors (parallel pat- terns) with clock speeds up to 25 MHz for functional testing and troubleshooting.
Page 12: Bus Emulation
9100A-017. Several new Test Language (TL/1) functions have been added to make use of the new capabilities of the 9100A-017. Loading the vectors from the 9100A hard disk to each module during pro- gram execution requires a maximum of 3 seconds, with 1 sec-...
Page 13: User Operations
9100A-017 USER OPERATIONS 1.5. Users may access the new Vector Output I/O Module through functions provided in the Operator’s Interface, TL/1, and the Editor. From the Operator’s Interface, all the input functions of the original 9100A-003 Parallel I/O Module are still available for the new Vector Output I/O Module.
Page 14 9100A-017...
Page 15: Specifications
Section 2 Specifications SPECIFICATIONS 2.1. Table 2-1 contains the specifications for the Vector Output I/O Module. NOTE Output specifications for Table 2-1 were obtained using the Y9100-102 Card Edge Interface Module into 10 LSTTL loads. Results may vary depending on the impedance, length, and shielding of the connector used.
Page 16 9100A-017 Table 2-1. Vector Output I/O Module Specifications (cont) Clock to Vector Out (tdel): INT CLK Out to Vector Out Delay .....37 ns typical, 45 ns maximum. DR CLK in to Vector Out Delay......50 ns typical, 58 ns maximum. WAIT (Handshake) Setup Time (twsu) ....42.5 ns maximum (35 ns typical) from WAIT acknowledgement until next dock cycle drives vector.
Page 17 9100A-017 Table 2-1. Vector Output I/O Module Specifications (cont) VECTOR OUTPUT I/O MODULE INPUT SECTION: Input Impedance ........... 50 KΩ Minimum, 90 KΩ typical. 100 pF Maximum, 65 pF typical. * Operating Voltage Range........-0.5V to +5.5V (all lines) Input/Output Protection ......... +10V/-5V for one minute max. one line only (all lines).
Page 18 9100A-017 Table 2-1. Vector Output I/0 Module Specifications (cont) Stop Edge Setup Time (before clock edge, for clock edge to not be recognized)....5 ns minimum Enable Setup Time (before clock edge, for clock edge to be recognized)....0 ns minimum Enable Hold Time (after clock edge, for clock edge to be recognized)....10 ns minimum...
Page 19: Vector Output Operation
Section 3 Vector Output Operation INTRODUCTlON 3.1. This section describes the general functions of the Vector Output I/O Module. Each of these functions are covered more fully in the Sections that follow. CLOCK SELECTION 3.2. The Vector Output I/O Module can be synchronized to a number of different clock sources, both external and internal.
Page 20: Vector Loading
9100A-017 To synchronize response gathering, connect the Vector Output I/O Module input CLOCK line to the INT CLK output and set the sync command to “ext”. Another method would be to use the TL/1 sync “capture” mode. This method allows you to pro- gram clocks into the vector file to determine when data is gath- ered in the input section of the I/O Module.
Page 21: Stopping Vector Driving
9100A-017 transition has occurred, vector driving resumes on the next qualified clock. The edge polarity cannot be changed from one polarity to the other within the vector file. STOPPING VECTOR DRIVING 3.7. Vector driving is stopped if the STOP statement is reached in a...
Page 22: Tristate Control
9100A-017 TRISTATE CONTROL 3.8. A low signal on the TRISTATE input line of the Vector Output I/O Module asynchronously tri-states the 40-pin output of the module. The output of the module remains tri-stated after the removal of the TRISTATE low signal until a writeword or writepin command has been executed or further vector driving has occurred.
Page 23: Completion Status
9100A-017 COMPLETION STATUS 3.9. The drivepoll command determines the completion status of vector driving. Two bits are returned from a drivepoll com- mand: Bit 1 indicates if vector driving is currently suspended while awaiting the programmed WAIT edge (0 for waiting, 1 for...
Page 24 9100A-017...
Page 25: Hardware
Section 4 Hardware PHYSICAL DESCRIPTION 4.1. The 9100A-017 Vector Output I/O Module connects to the 9100A/9105A Mainframe through a round shielded cable, and connects to the UUT or fixture through a variety of I/O Module clip modules and measurement control lines.
Page 26 9100A-017 been executed. The COMMON lead should always be connected to the UUT except during self test and calibration. On the right side of the Vector Output I/O Module is a 6-pin connector. These pins perform the following functions: •...
Page 27 9100A-017 • COMMON System common. This pin should be connected to the UUT if any of the other pins on this part of the Vector Output I/O Module are used. • INT CLK The internal clock specified by “intclk” in the syncoutput command is output on this line.
Page 28 9100A-017 Figure 4-1. Vector Output I/O Module Block Diagram Figure 4-2. Vector Output I/O Module Output Section...
Page 29: Connecting The Module To The Mainframe
9100A-017 Figure 4-3. Input Section Block Diagram CONNECTING THE MODULE TO THE MAINFRAME 4.2. Before performing the Vector Output I/O Module self test or calibration, connect the module to the 9100A/9105A Mainframe as follows: Check that the Mainframe is OFF.
Page 30: Performing The Module Self Test
9100A-017 PERFORMING THE MODULE SELF TEST 4.3. The Vector Output I/O Module self test determines if the selected module(s) is connected to the Mainframe and is communicating with the system. Perform the following steps to begin the self test: Remove any clip modules from the Vector Output I/O Module.
Page 31: I/O Module To External And Capture
9100A-017 Calibration should be done when the system is first set up and at regular intervals (at least monthly). Calibration is also necessary whenever devices attached to the system are changed or re- paired. Once the calibration is complete, the calibration data can be saved and restored when needed.
Page 32: I/O Module To Pod
9100A-017 Press the ready button on the calibration module. When the calibration is complete, the BUSY light on the Mainframe goes off and the display reads: MAIN: CALIBRATION COMPLETE I/O Module to Pod 4.6. This calibration calculates the proper settings for the Vector...
Page 33: Connecting The Module To The Uut
4.7. Using the Clip Modules 4.8. The same clip modules can be used with the 9100A-017 Vector Output I/O Module as are used with the 9100A-003 Parallel I/O Module. The clip modules therefore connect to the UUT in the same way as with the Parallel I/O Module. However, because...
Page 34: Connecting The External Lines
Using the Card Edge Fixture Kit 4.10. The Card Edge Fixture Kit (John Fluke model number Y9100A- 100) provides a simple means to interface the 9100 test system to boards with card-edge connectors. The kit enables up to four Vector Output I/O Modules to be connected to a card edge.
Page 35: Synchronizing The Module To The Uut
RAM control circuitry, or for other purposes. The Card Edge Fixture Kit manual (John Fluke part number 830349) contains further application and fixturing information that is not only useful for the fixture kit, but for general applications as well.
Page 36 9100A-017 NOTE The enabling condition need not always depend on the specified state (HIGH, LOW, ALWAYS) of the Enable input. The enabling condition can also involve the state of the internal PodSync line. After an ARM I/O MOD command is entered and after a valid Start edge is detected, the measurement period begins.
Page 37: Pod Sync Mode
9100A-017 • Transition counter. Records each rising transition at the input, between Start and Stop, while enabled. A rising transition is either 0-to-1 or X-to-l. For more information, see the sync command in Section 3 of the TL/1 Reference Manual and the SYNC key in the Technical User's Manual keypad reference section.
Page 38: Freerun Sync Mode
9100A-017 • Clocked level history registers. • Asynchronous level history registers. • Transition counter. The data is gathered as described previously in External Sync Mode, except that the CRC signatures and clocked level history are clocked by the internal pod signal.
Page 39: Capture Mode
9100A-017 Capture Mode 4.16. The capture sync mode synchronizes the response gathering hardware with the vector output automatically. When the vector files are edited, vectors can be programmed to clock the input section on a single vector, specific vectors, or all vectors. For more information, refer to Section 6 of this manual for the cap- ture command description.
Page 40: Synchronizing Multiple Module Vectors
9100A-017 becomes critical as clock speeds increase above 5 Mhz. This duty cycle ensures that the the minimum clock pulse width of 50 ns is maintained. If the clock does not have a duty cycle close to 50%, the external sync mode is recommended instead of the capture mode for high speeds.
Page 41: Tl/1 Functions
Section 5 TL/1 Functions INTRODUCTION 5.1. Eight new functions have been added to the 9100A Test Language (TL/1) to support the new Vector Output I/O Module. This section briefly describes each of these new functions. See Appendix A for a complete description of the functions. Figure 5-1 illustrates the relationship between the TL/1 commands and the Vector Output I/O Module operations they affect.
Page 42: Edgeoutput
9100A-017 Figure 5-1. Vector I/O Control NOTE If an external stop signal has been received and is enabled, the vector driving terminates, but drive- poll does not indicate vector driving as complete. EDGEOUTPUT 5.4. The edgeoutput function sets the signal edges for triggering the START, STOP, and DR CLK lines.
Page 43: Enableoutput
9100A-017 ENABLEOUTPUT 5.5. The enableoutput function controls the enabling (or qualifying) of the vector drive clock. If the enable is not received, the vector count remains at the current vector regardless of the clocks received until the clock is enabled. Only syncoutput modes “drclk”...
Page 44 9100A-017...
Page 45: Using The Vector Editor
Using the Vector Editor INTRODUCTION 6.1. To be able to drive vectors out the 9100A-017 Vector Output I/O Module, a vector file must be created. This file contains all the information required by the module to output the proper se- quence of signals.
Page 46: Softkey Operations
9100A-017 Whenever a vector file is created, the text at the top of the file is automatically produced. When loading a previously created file, nothing is added to the file. Once the file is loaded, use the standard editor functions to enter new data.
Page 47 9100A-017 • F5 - Cut Deletes the marked block from the display and moves it into one of the temporary buffers. This softkey does not appear until a Mark has been set. See the 9100 Series Programmer’s Manual for more information.
Page 48: Working With The Vector File
9100A-017 WORKING WITH THE VECTOR FILE 6.4. When a vector file is first created, four lines of text are automati- cally created at the beginning of the file. These four line are: GROUPS [40-1] DISPLAY BIN !TIME DATA The first line is called the groups line. The second line is called the display line.
Page 49: The Display Line
9100A-017 through 4 and pin 6, and put the rest of the pins in another group, the groups line would be changed to read: GROUPS [1-4,6][5,7-40] Note that the groups line in the previous example did not use the optional <label>. If, however, you want to add a label that...
Page 50: Comment Lines
9100A-017 and you want the first group to be displayed in hexadecimal and the second group to be displayed in binary, you would change the display line to read: DISPLAY HEX, BIN If more than one group exists in the groups line and both are to be displayed as hexadecimal, only one designator is necessary.
Page 51 9100A-017 Using the first four lines that appear when the vector file is cre- ated, a data field may be entered that looks like: GROUPS [40-1] DISPLAY !TIME DATA 1 1000000010001000100000000001111111110111 The data field in the previous example must be 40 characters long and is entered in binary format.
Page 52 9100A-017 Press the F3 (RENUM) key to renumber the lines while editing. To fill a data field line when there is more than one group on the groups line, you must enter the data with a space separating the groups. For example, the following vector file contains two...
Page 53 9100A-017 the editor would display the file as: GROUPS [40-9] [8-1] DISPLAY HEX, BIN !TIME DATA 1 $401007FD 1111XXXX The “$” sign that was added to the data field line indicates a hex- adecimal number. The second field is still in binary notation.
Page 54 9100A-017 If the groups line or the display line are modified after data fields have been entered into the file, the data fields change to match the modifications. For example, if the following vector file was loaded: GROUPS [40-9] [8-1]...
Page 55: Control Phrases In Data Fields
9100A-017 On line 3, the binary representation in the second field could not be converted to a hexadecimal representation, so the “*” charac- ter was added to the beginning of the field to retain its binary representation. Control Phrases in Data Fields 6.9.
Page 56 9100A-017 Capture Capture On Capture Off The Capture phrase causes the input section to be clocked on the opposing edge of the selected output clock (which causes the clocking to occur near the center of the preceding vector). Only one capture should be used for a single data field (i.e., you can place two capture statements...
Page 57 9100A-017 3 1111110001101010100001010010101010000111 4 0000000000000000000000000000000000000000 5 1111111111111111111111111111111111111111 ENDLOOP and the vectordrive command specifies that the file begins driv- ing on data field 4, the vectors are driven out in the order - 4, 5, 2, 3, 4, 5, 2, etc.
Page 58 9100A-017 6-14...
Page 59: Applications
Section 7 Applications USING THE VECTOR OUTPUT I/O MODULE 7.1. The Vector Output I/O Module can be used in a wide variety of applications, from simple pattern stimulus to performing bus cycles such as read and write cycles. Regardless of the application, five main steps are required to fully use the capabilities of the module.
Page 60: Bus Emulation
9100A-017 ****************************************************************************** program example devname - "/mod1" reset device devname setword device devname, word 1, as_pins "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40"...
Page 61 9100A-017 A logic analyzer may also be useful for determining cycle infor- mation. The logic analyzer can be connected to a known-good system with the UUT plugged into a motherboard so the cycles can be observed. The analyzer can also provide other informa- tion (such as initialization sequences, handshaking protocols, etc.) that may be necessary to perform bus communication.
Page 62: Testing The Ibm Cga Video Card
9100A-017 TESTING THE IBM CGA VIDEO CARD 7.3. The Vector Output I/O Module can test bus-based UUTs that do not have an on-board microprocessor. The key to testing this type of board is to determine the vector patterns necessary to perform the required bus cycles.
Page 63: Fixturing The Cga Interface
9100A-017 Fixturing the CGA Interface 7.4. Table 7-1 maps the pins and signal names of the CGA Card with the pins of the Vector Output I/O Module. To accomplish the fixture design and vector bus cycle pro- gramming, you must use the specifications for the MC6845 CRT Controller and the information on the CGA Card contained in the IBM Technical Reference Manual.
Page 64: Fixturing Considerations
9100A-017 Fixturing Considerations 7.5. Fixturing between the Vector Output I/O Module and the CGA Card is minimal. To keep line lengths as short as possible and to keep interfacing easy, the Y9100A-102 Card Edge Interface Module is recommended. Most lines from the card edge module to the CGA card-edge connector match except for the following: •...
Page 65 9100A-017 MC6845 CRT CONTROLLER BUS CYCLES 7.7. Examine the timing diagram for the MC6845 (shown in Figure 7-1) to determine the vector patterns necessary to achieve the required bus cycles. To perform a read/write cycle, the following conditions must be met: •...
Page 66 9100A-017 vector period is 167 ns. Vector 1 sets the address and control data. Vector 2 is driven out 167 ns later. IOW is set low so that, on the next clock cycle, the E clock will be set high. To ensure that the E clock remains high for the required time, vector 3 and 4 are driven.
Page 67 9100A-017 high for two cycles (334 ns) to ensure that the data held on the bus is valid. Using the TL/1 readword command in the “stored” mode will return the data read. CRT Controller Read Cycle Vector File GROUPS [40-21][20-13][1][2][3][4][5][7][8][6][12-9]...
Page 68: Vector File Generation
9100A-017 2 $B8000 XXXX WAIT + 3 $B8000 XXXX STOP In the Video RAM Read Cycle Vector File that follows, vector 1 sets addresses A19 through A0 and data D7 through D0 to tri- state. Vector 2 holds the address and data while MEMR goes low.
Page 69: Cga Write/Read Program Example
9100A-017 addition to performing writes and reads to the CGA Card, the 9100 probe and clock module can take signatures of the RGBI outputs to test the outputs. CGA Write/Read Program Example 7.10. The following program initializes the CGA Card in the 80 column character mode, fills the screen with ASCII characters, and then reads back two locations.
Page 70: 68000 Bus Video Application
9100A-017 end function ! **************************************************************************** ! This is the main program body. ! **************************************************************************** devname - "/mod1" ! *****Define Word To Match D7 - D0***** setword device devname, word 1, as_pins "20 19 18 17 16 15 14 13" ! *****Reset PC CGA Card***** writepin device devname, pin 7, level "1", mode "latch"...
Page 71: Fixturing The Video Board Interface
9100A-017 Fixturing the Video Board Interface 7.13. Table 7-2 maps the pin and signal names of the Video Board with the pins of the Vector Output I/O Module. Table 7-2. Video Board to Vector Output I/O Module Mapping Module Module...
Page 72: Determining Bus Cycles
9100A-017 gate whose output is connected to WAIT. If either signal goes low, the WAIT input will go low as well. For trou- bleshooting in the case of no DTACK, both the VDTACK and VWAIT lines should also be connected to Vector Output I/O Module pins where their activity can be moni- tored.
Page 73 9100A-017 Figure 7-2. SCN2674 Controller Timing Diagram (4 MHz Version) • CE (which is controlled by PS7) has a setup time of 0 ns prior to R/W going low. • WR has a minimum pulse width of 200 ns. •...
Page 74: Determining The Read Cycle
9100A-017 2674 Video Display Controller Write Cycle GROUPS [40-30,1][29-22][21-14][13][12][11][10][9][8][7][6][5-2] DISPLAY HEX,HEX,HEX,BIN ADDR DATA CTRL UNUSED All - Al D15-D8 D7-D0 (A0) ! WRITE CYCLE addr $f0013, data $XX00 (addr $fxxxx = PS7-, data $XX00 = LDS-) 1 $013 XXXX 2 $013...
Page 75 9100A-017 • CE (which is controlled by PS7) has a setup time of 0 ns prior to RD going low. • RD has a minimum pulse width of 200 ns. • Data D7 through D0 will be valid a maximum of 100 ns after RD goes low.
Page 76: Wait Application
9100A-017 results are not stable, the setoffset command should be used to delay the data read with respect to the clock. An alternative method would be to add one more vector to hold RD and CE low while the capture is performed before returning RD and CE high.
Page 77: Timing Sets
9100A-017 the line on the vector would provide the edge necessary to sat- isfy the WAIT. If the controlling signal was not at the desired level, vector driving would halt until the signal was set to the correct level. Figure 7-3. Using WAIT to Check for a Level (Method 1) Another method would “AND”...
Page 78 9100A-017 number of times the cycle is to be repeated. One output line of the first module would be connected to the second module's DR CLK line to clock out the address and data vectors (as shown in Figure 7-5).
Page 79: Tl/1 Vector File Generation
9100A-017 Module 1 Vector File (Timing Sets) GROUPS [25][26][27][28][29][30][31][32][16-9][8-1][24-17][33-40] DISPLAY BIN,BIN,BIN,BIN,BIN,BIN,BIN,BIN,HEX,HEX,HEX,HEX UNUSED 0 $XX LOOP 5 ! START OF WRITE CYCLE 1 $XX 0 $XX WAIT - 0 $XX 0 $XX ENDLOOP STOP Module 2 Vector File (Address/Data Information) GROUPS [16-9][8-1][24-17][25-40)
Page 80 9100A-017 template (such as the following Write Cycle Text File). A second text file can be made that contains the address and data to be inserted into the bus cycle (such as the following Address Data Text File). A program (such as the example “build” program),...
Page 81 9100A-017 program build ! **************************************************************************** The build program is used to generate textfiles that may he coerced into vector files. It is necessary to have a textfile "WRITECYCLE" which contains a description of a single write cycle. The user will be prompted to enter the text file name which contains the address and data information and the text file name to which the file is to he written to.
Page 82 9100A-017 ! **************************************************************************** This is the main program body. ! **************************************************************************** ! *****open devices, print screen***** t2u = open device "/term2", as "update" t2o = open device "/term2",as "output" print on t2o, "\1B[H\1B[J" ! *****get existinq cycle information***** ! *****this example has 17 lines in the writecycle file***** ! *****which are stored in writecyc string array***** if (filestat file "writecycle") <>...
Page 83: New Tl/1 Commands
Appendix A New TL/1 Commands...
Page 84 9100A-017...
Page 85 clockfreq Syntax: clockfreq [device <device list>] [, freq <freq>] clockfreq (<device list>,<freq>) clockfreq() Syntax Diagram: Description: Sets the internal vector output drive clock frequency to 1 MHz, 5 MHz, 10 MHz, or 20 MHz. This command is used with the Vector Output I/O Module only. Arguments: device list I/O module name, clip name,...
Page 86 Example 1: ! Set clock frequency of /mod1 to 1MHz ! Set clock frequency of /mod2 to 5MHz ! Set clock frequency of /mod3 to 10MHz ! Set clock frequency of /mod4 to 20MHz clockfreq device "/mod1", freq "1MHz" clockfreq device "/mod2", freq "5MHz" clockfreq device "/mod3", freq "10MHz"...
Page 87 For More Information: • The “Overview Of TL/1” section of the Programmer’s Manual. clockfreq-3...
Page 88 clockfreq-4...
Page 89 drivepoll Syntax: drivepoll device <device list> drivepoll (<device list>) drivepoll() Syntax Diagram: Description: Returns the current drive and handshake status of the re- quested I/O module(s). This command is used with the Vector Output I/O Module only. Arguments: device list I/O module name, clip module name, or combination of these.
Page 90 Example 1: !Wait for drive and handshake to complete on !/mod1 vectordrive device "/mod1" loop while ((drivepoll device "/mod1") <> 3) end loop print "vector drive completed" Example 2: ! Use "/mod2" to supply the rising edge to ! "/mod1" each time a handshake is needed. writepin device "/mod2", pin 1, level "0"...
Page 91 For More Information: • The “Overview Of TL/1” section of the Programmer’s Manual. drivepoll-3...
Page 92 drivepoll-4...
Page 93 edgeoutput Syntax: edgeoutput [device <device list>] [,start<start edge>] [, stop <stop edge>] [, clock <clock edge>] edgeoutput (<device list>,<start edge>, <stop edge>, <clock edge>) edgeoutput() Syntax Diagram: Description: Specifies the active edge for the external START, STOP, and DR CLK inputs used to drive out vectors. Does not affect the input section hardware.
Page 94 clock edge External clock edge “+” or “-”. (Default = “+”) Example 1: mod = "/mod1" edgeoutput device mod, start "+", stop "- ", clock "+" Example 2: modlist = "/mod1,/mod2" edgeoutput device modlist, start "-", stop "-",clock "+" Remarks: The start edge argument “at_vectordrive”...
Page 95 enableoutput Syntax: enableoutput [device <device list>] [, mode <mode>] enableoutput (<device list>,<mode>) enableoutput() Syntax Diagram: Description: Specifies the level for the external ENABLE line used to qualify the clocks for vector driving. Does not affect the input section hardware. This command is used with the Vector Output I/O Module only.
Page 96 Example 2: enableoutput device "/mod4B", mode "always" Remarks: The enableoutput mode argument determines the clock qualifier used for vector driving. If the “always” mode is selected, all clocks are qualified to drive out vectors. If the “high” or “low” mode is selected, the appropriate level must be present on the external ENABLE line to qualify the clock.
Page 97 strobeoutclock Syntax: strobeoutclock device <device list> strobeoutclock (<device list>) strobeoutclock() Syntax Diagram: Description: The strobeoutclock command performs an internal clocking of a vector when the module syncoutput mode is set to “int”. Subsequent executions of the strobeoutclock command continues to drive vectors until the end of the vector file is reached.
Page 98 strobeoutclock device mod readout device mod crc = sig device mod, pin 1 lvl = level device mod, pin 1, type "clocked" Example 2: ! use "/mod1" to set up peripheral port at $90000 ! use pod to read results mod = "/mod1"...
Page 99 syncoutput Syntax: syncoutput [device <device list>] [, mode <sync mode>] syncoutput (<device list>,<sync mode>) syncoutput() Syntax Diagram: Description: Selects the vector output clock source. This command does not affect the input section hardware. The actual clock selection does not occur until the vectordrive command has been executed.
Page 100 Example 2: syncoutput device "/mod2", mode "pod" syncoutput device "/mod1", mode "drclk" vectordrive device "/mod1, /mod2" Remarks: When the syncoutput mode is set to “pod”, use the sync command to select either pod address, pod data, or an- other pod sync mode as the clock source. When the syncoutput mode is set to “intfreq”, use the clockfreq command to control the frequency of the clock.
Page 101 vectordrive Syntax: vectordrive [device <device list] [, startmode <startmode>] [, vector <vector>] vectordrive (<device list>,<startmode>,<vector>) vectordrive() Syntax Diagram: Description: The execution of this command enables the loaded vector file to be driven, starting at the indicated vector. This command is analogous to an “arm” command for the output. This command is used with the Vector Output I/O Module only.
Page 102 vector Vector number from which to begin driving (from 1 to the number of vectors loaded). The vector number directly corresponds to the vector number in the vector file. (Default = 1) Example 1: vectorload device "/mod1", file "vec1" vectordrive device "/mod1", startmode "now", vector 1 Example 2: vectorload device "/mod1", file...
Page 103 If startmode is “at_arm”: the same conditions apply as above, except that the TL/1 arm command must be executed first (to permit simultaneous arming of the vector driving and the response gathering hardware). Once loaded, a vector file can be driven repeatedly, starting at any specified vector, until overwritten by a writepin or writeword command.
Page 104 vectordrive-4...
Page 105 vectorload Syntax: vectorload [device <device list>,] file <file name> vectorload(<device list>, <file name>) Syntax Diagram: Description: Causes the vector file “filename” to be loaded into all modules designated in <device list>. A single vector file cannot cover more than one I/O Module. However, vectorload may load the same file into several modules at the same time.
Page 106 Example 2: vectorload device "/mod1", file "vec1" vectordrive device "/mod1" Remarks: Whenever a vectorload command is executed, all vectors currently in the designated I/O Module are removed and the new vector file is loaded. The file remains in the designated I/O Module until overwritten by execution of the writeword or writepin commands, or until another file is loaded.
Page 107 For More Information: • The “Overview Of TL/1” section of the Programmer’s Manual. vectorload-3...
Page 108 vectorload-4...
Page 109: I/O Module Clip/Pin Mapping
Appendix B I/O Module Clip/Pin Mapping Clip size = 14, module installed on "A" side Clip I/O Mod Pin Clip I/O Mod Pin Clip size = 14, module installed on "B" side Clip I/O Mod Pin Clip I/O Mod Pin...
Page 110 9100A-017 Clip size = 16, module installed on "A" side Clip I/O Mod Pin Clip I/O Mod Pin Clip size = 16, module installed on "B" side Clip I/O Mod Pin Clip I/O Mod Pin...
Page 111 9100A-017 Clip size = 18, module installed on "A" side Clip I/O Mod Pin Clip I/O Mod Pin Clip size = 18, module installed on "B" side Clip I/O Mod Pin Clip I/O Mod Pin = 21 = 22 = 23...
Page 112 9100A-017 Clip size = 20, module installed on "A" side Clip I/O Mod Pin Clip I/O Mod Pin Clip size = 20, module installed on "B" side Clip I/O Mod Pin Clip I/O Mod Pin...
Page 113 9100A-017 Clip size = 24, module installed on "A" side Clip I/O Mod Pin Clip I/O Mod Pin Clip size = 24, module installed on "B" side Clip I/O Mod Pin Clip I/O Mod Pin...
Page 114 9100A-017 Clip size = 28 Clip I/O Mod Pin Clip I/O Mod Pin Clip size = 40 Clip I/O Mod Pin Clip I/O Mod Pin...
Page 115: Keypad Reference Changes
Appendix C Keypad Reference Changes This appendix lists the changes made to the keypad reference syntax to accommodate the 9100A-017 Vector Output I/O Module. Only the MAIN MENU key and the SYNC key are changed.
Page 116 9100A-017...
Page 117 9100A-017...
Page 118 9100A-017...
Page 119 Index 68000 video applications, 7-12 arm, 4-14, 5-3 Asynchronous level history register, 4-14 Block diagram overview, 4-3 Block reads, 7-3 Bus emulation, 7-2 Cable length, 4-9 Calibrating the module, 4-6 Calibration module, 4-8 Capture, 4-7, 6-12 Capture mode, 4-15 Card edge fixture kit, 4-10 Card edge interface module, 4-10 CGA Mapping, 7-5 CGA Program Example, 7-11...
Page 120 9100A-017 CTS, 7-18 Cyclic redundancy check, 7-3 Data Compare Equal, 7-3 Data fields, 6-6 DCE, 4-3 Determining bus cycles, 7-14 Determining the read cycle, 7-16 Determining the write cycle, 7-14 Display line, 6-5 DR CLK, 4-2, 4-16 drivepoll, 5-1, Appendix A...
Page 121 9100A-017 Operating temperature, 2-4 Output section, 4-3 Overdrive, 1-3 Physical specifications, 2-4 Pod, I/O Module to, 4-8 Pod sync mode, 4-13 Program example, 7-2 Read cycle, 7-3 readout, 4-14 Ready button, 4-1 Receive section, 4-3 Self test, 4-6 Softkey operations, 6-2...
Page 122 9100A-017 Vector loading, 3-2 Vector output clock source, Appendix A Vector output operation, 3-1 vectordrive, 5-3, 6-7, 6-12, Appendix A vectorload, 5-3, Appendix A Video RAM bus cycles, 7-9 WAIT, 3-2, 4-2, 5-1, 6-12 WAIT application, 7-18 Working with the vector file, 6-4...

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9100a series

Fluke 9100A-017 Manual

1 Introduction

2 Specifications

3 Vector Output Operation

4 Hardware

5 TL/1 Functions

6 Using the Vector Editor

7 Applications

New TL/1 Commands

I/O Module Clip/Pin Mapping

Keypad Reference Changes

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