Internal Signal Routing; Redundant Antivalent Signal Logic With Discrepancy Analysis - Siemens SIDOOR AT40 System Manual

6.3.3.1

Internal signal routing

The following figure illustrates the input terminals and the internal wiring to the processor.
The input signals are located at processor port M. Separate reference potentials 0M, 1M and
2M can each be defined for Input 2, Input 3, Input 4 and for Input 1 and Input 0. The input
signals are provided with internal pull-ups and there are no components between the input
terminals and the processor that are capable of oscillation.
①
0M Ground potential 1
1M Ground potential 2
2M Ground potential 3
Image 6-9
6.3.3.2

Redundant antivalent signal logic with discrepancy analysis

In the case of 1oo2 evaluation, the sensor is routed to two different, mutually antivalent
channels and is therefore evaluated by the controller twice. The discrepancy analysis is
performed between the two channels of the 1oo2 evaluation in the controller. If there is a
discrepancy between the input signals after expiry of the parameterized discrepancy time,
e.g. due to breakage of a sensor cable, the internal signal is set to "0". The discrepancy
analysis at the input channels is performed with the "AND0" discrepancy analysis block (see
Section Auto-Hotspot). This special kind of signal routing achieves PLd and enables both
high availability and error detection.
The following graphics show an example of 2-channel antivalent wiring of a sensor
(antivalent).
AT40, ATD400V, ATD400K, ATD4xxW, ATD400S, ATE250S, ATD400T
System Manual, 06/2016, A2B00096162-AN
No components capable of oscillation and internal pull-up circuit
Internal wiring of input terminals
Controllers
6.3 Safety concept ATD4xxW
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