Memory - HP 400 Series Servicing Manual

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DMA DIO Controller
The DMA controller is programmable for byte, word, and 32-bit transfers. This con-
troller supports DMA transfers for the SCSI and Centronics parallel interfaces.
3.2.2

Memory

Memory boards for Series 400 systems are available in 2-, 4-, and 16-MB board con-
figurations. The 2- and 4-MB boards consist of 1 Megabit (Mb) DRAMS. The 16-MB
board consists of 4-Mb DRAMs, in a 4-bit wide configuration. Memory boards must
be used in like pairs to form a memory block (for example, two 2-MB memory boards
form a 4-MB block). These board pairs must reside in a high-to-low configuration,
beginning with the lowest numbered memory slots on the CPU board. For example, if
a Model 400s system uses a 32-MB board pair and an 8-MB pair, the 32-MB pair al-
ways resides in the two lowest-numbered slots (0A and 0B), and the 8-MB pair always
resides in the third and fourth slots (1A and 1B). Do not allow empty slots between
boards.
The three Series 400 systems use different memory boards and memory configurations:
• The Model 400t can use 2- and 4-MB boards, for memory configurations of 8
• The Model 400dl can use 4-MB boards, for a memory configuration of 8 or 16
• The Model 400s can use 4- or 16-MB boards, for memory configurations of 8
Memory design includes a memory data path that supports 8-bit Error Checking and
Correction (ECC) on a 64-bit data word. The ECC logic is located on the data path
between the RAM arrays and the processor or alternate bus master. This logic corrects
single bit errors, and detects all double bit errors, and triple and quadruple bit errors
grouped in nibbles. The system displays the message, "
Detected
ter 4 for more information about error codes). The memory controller decodes the ad-
dress space occupied by memory, interprets the types and sizes of transfers, and gener-
ates signals and timing to the DRAMs. The controller also provides all control signals
to the ECC logic.
Provides Multimap DIO-I accesses to system memory and the DIO-II inter-
face for system memory
Performs dynamic bus sizing for the CPU
to 32 MB in 4- or 8-MB increments.
MB.
to 128 MB in 8- or 32-MB increments.
" in the event of these double, triple, and quadruple bit errors (refer to Chap-
Uncorrectable Memory Error
Theory of Operation 3-15