Panasonic JB-3300 Technical Manual page 308

Figure 4-2 shows a sample output of KBDATA and KBCLK, when KBDATA = H
(keyboard output permitted by the system unit) and KBCLK = H (the
unit does not request keyboard self test). The KBDATA response to
the key operation is shown in Figure 4-3. This output is controlled
by microprocessors P10 and Pll.
Figure 4-4 shows the timing of KBCLK and KBDATA.
t
| "3 4 |
I 1
_ 'TYPpUDUYYPUD Wo
ct
KBDATA —=t=— "2
Start (LSB) (MSB) Stop Bit
Bit (Make: 0
:1 t =9us Break:1)
1
t. = 22 Us
t. = 31 Us
ty = 103 Us
Figure 4-4 Timing of KBCLK and KBDATA
A unit of data from KBDATA consists of a start bit and 8 data bits
followed by a stop bit. The 8-bit data is arranged from LSB to MSB.
As Figure 4-5 shows, KBDATA output is inhibited for 6 ms after it has
been output.
Approx. 6 ms
KBDATA ee
Figure 4-5 KBDATA Output Inhibit
Iv - 8