Panasonic JB-3300 Technical Manual page 160

The I/O operation is described below.
An I/O address sent from the CPU is decoded by ROM 24S10. Table 5-2 shows
the ROM data. The CPU status signal *BSO and the DMA status signal
*AENCPU enable the 24510 to decode addresses. The decoder IC LS138
outputs a SELECT signal to each I/O using the 24S10 output and part of the
address bus.
— Color/Graphics
- Ti (Plasma Display)
Parallel Port
0378
O2FF
O2F8
027F LLLLLLLZ_
Qoeremnscnesd
———- Hard Disk
Asynchronous Communications*
Parallel Port*
PIC 8259A
. Basic I/O 4 TIMER 8253-5
PPI 8255A-5
DMA Page Register
NMI Mask Register
0000
* Switchable
Figure 5-19 I/O Address Map
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