Video Ram Configuration And Display Dots - Panasonic JB-3300 Technical Manual

2.
The SYNC and address signals output by the CRTC refresh the PDP display.
The CRTC outputs screen addresses (CMA13 to CMAO) and raster addresses
(RA3 to RAO) to show positions to be displayed on the screen. The video
RAM contents are accessed with these addresses to read display data, which
is converted into video signals in the PDP interface for display on the
PDP.
The data from the video RAM is read in two-byte units. In the text
display mode, data corresponds to display character and attribute codes,
while in the graphic display mode, data corresponds directly to graphic
display dots.
The character generator ROM is accessed and display dots corresponding to
display character codes and raster addresses are obtained in the text
display mode to convert display character codes into display dots.
Display dots are further divided into l-digit (4-bit) units and are input
to the video generator, which outputs these display dots as video signals
to the PDP, after adding gualifications such as attributes and color
designation.
The MPU writes in or reads from the video RAM by refreshing the display
while the video RAM is not accessed, i.e., is idling.
The PDP controller outputs a WAIT signal to hold the MPU static while the
video RAM has idle time, in case the MPU accesses the video RAM. The
video RAM is accessed b switching the video RAM address from the CRTC to
an MPU address with the address multiplexer when the video RAM is idle.
The output of the WAIT signal to the MPU is stopped simultaneously to end
video RAM accessing by the MPU.
Video RAM configuration and display dots
The PDP controller has a 32K-byte video RAM for a dedicated display
memory.
The video RAM has been allocated addresses for 32K bytes, B8000 (HEX) to
BFFFF (HEX).
The internal configuration of the video RAM varies with the display mode.
Figure 4-3 shows a video RAM configuration.
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