Table of Contents
Advertisement
*CRT CASO
Ls
L4
*CRT CAS1
L
LY
;
:
DATA
ATA
VRAM #0 Data
DaTAin))
(nt2)
(nt)
in+6)
Sl
\
|
Isr Data Latch
,
| DaTA(n)
,
\
DATA (n#4)
|
2nd Data Latch
Na
DATA (n+2)
|
» DATA (n+6)
EN EVEN
|
\
| \
|
|
|
CHBO to 7
:
=F
ODATA In)
X
DATA (n+2)
C=
vataint+4) XK
DATA (n+6)
)
|
)
|
DATA
DATA
DATA
VRAM #1 Data
(PATA
(n+3
(n+5)
(n+7)
|
| \
I \
ist Data Latch
\
DATA (n +1)
M
?
\
DATA (n+5)
2nd Data Latch
x !
+t
DATA (n+3)
C
;
DATA (n+7)
EN EVEN
|
|
|
|
|
|
| \
|
!
ATBO to 7
=X paTaint+i) ~ ~ X
DATA (n +3)
=X vata in+5) XK
DATA (n+7)
Figure 5-48
Timing Waveforms
(TEXT 80x25)
- Quick Links:
- Table of Contents
Hide quick links:
Advertisement
Table of Contents
Troubleshooting
