Panasonic JB-3300 Technical Manual page 223

(e)
Floppy disk interface
The blocks are outlined below.
O
FDC (NEC uPD765)
This is an LSI having a floppy disk formatter/controller function.
Placed between the floppy disk drive and the microprocessor, this
interface reads and writes data on floppy disks, drives the
mechanical section, and detects control signals.
Refer to the FDC data sheet for more detail.
FDD control command register buffer
This is an FF circuit set with an I/O instruction. This buffer
designates Drive Select, Motor Start, FDC Reset, or DMA
Permission.
DREQO controller
This controller creates an interface timing between DMAC and FDC
in DMA transfer.
Clock generator
This generates a 16-MHz clock frequency, and supplies it to the
FDC and the VFO.
The frequency is first supplied to the VFO, where it is
frequency-divided into a 4-MHz clock, and supplied to the FDC.
VFO circuit
This circuit separates data read from the floppy disk into data
and clock, and creates data and windows.
Refer to the data sheet for details on the VFO LSI (SED9420C).
Precompensation circuit
This circuit prevents erroneous data read, which may occur when
the write data peak shifts during magnetic recording.
Power-off reset circuit
This reset circuit functions at a voltage below 4.4 V to prevent
error data from being written into the floppy disk.
II - 103