Panasonic JB-3300 Technical Manual page 227

SC (LS175 |
PIN 15)
ee
5C PIN 7
5C PIN 2 (4) |
Precompensation circuit
This circuit advances or delays data writing by 250 ns to obtain
an time allowance during a read. It also acts as a gate for
step signals.
Figure 5-77 shows a timing chart. The output signal WDA (write
data) from the FDC synchronizes with the 4-MHz clock CLK in IC
LS175 and is delayed by 250 us. IC153 determines, using PSO and
PS1, which signal of LS175 should be selected.
The selected signal is resynchronized by LS175, and output to
the FDD as a precompensated signal.
250 =
—{
PSO. 1
\\
@
GB) { |
Figure 5-77 Precompensation Timing Chart
It - 107