Panasonic JB-3300 Technical Manual page 204

(2) HSYNC circuit
The HSYNC circuit receives the HSYNC signal from CRTC and
generates from it an HSYNC DLY signal (to be output to the
plasma display) and a status signal HSYNC STA.
Figure 5-57 shows an HSYNC circuit diagram.
+5V
=
ILS 7416/6)
|
(5-5E&) HSYNC
(6-3F) XCLK i I
HSYNC OLP
(I-10D) XRESET HSYNC STA
Figure 5-57 HSYNC Circuit
(3) VSYNC circuit
The VSYNC circuit receives the VSYNC signal from CRTC and
generates from it a VSYNC DLY signal (to be output to the plasma
display).
Figure 5-58 shows VSYNC circuit diagram.
RAQ
+5V |
+5V Lsti2 H_Lsos Tesii2
J>Q i2u- -a VSYNC DLY
I2J i2G
VSYNC —_, eK —dot
iD /LSO8
2'2Gie [A " <
| | K 12H J15 a
2 S393
RA'l
uf Io
tH m= XV SYNC (8A) (3F)
HSYNCDLY — LSO4
Figure 5-58 VSYNC Circuit
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