Panasonic JB-3300 Technical Manual page 148

(d) NMI (non-maskable interrupt) generation circuit
This circuit generates an NMI under following conditions:
Oo With co-processor 8087 installed and 8087 interrupt enabled, an
unmasked interrupt occurs during numeric instruction execution.
o The *IOCHCK signal is activated due to abnormal operation of the
memory in an expansion unit or of other optional device.
The operation is outlined below.
8087 NMI Enable Block
}
1 (2-4D) NPINSTL
8088
|
NM 1
(X50) NPNMI
De ee ee ee ee ee ee ee ee ee ee/
(X7D) DO7
(x10G) XWTNMI!
ly
RESET | _ _ ise
_ _ (X100)XRESET—-—--—= S35 4
+5V
|
|
r HI 10 5
| (2-38) XENBIOCH —Hfs>
LSO4
|
] 4
Vee ee ee
Parity Enable Block
Figure 5-10 NMI Generation Circuit
(1) NMI register
NMIs are enabled with this register.
I/O address: OOAO HEX
Command: To enable, S80OHEX (OUT)
To disable, QOHEX (OUT)
(2) 8087 NMI ENABLE BLOCK
Setting DIP switch #2 to OFF enables NPNMI for faulty operation
of the 8087.
If - 28