Panasonic JB-3300 Technical Manual page 207

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Plasma reset circuit
The plasma reset circuit enables/disables the plasma display. The
PDPCLR signal goes HIGH, and disables the plasma display in the
following two cases:
o When the CMDSET signal is LOW -- i.e., after power on and until
the display mode register is set.
o When the DETECT OPEN signal is LOW -- i.e., when the display is
closed.
Figure 5-62 shows the plasma reset circuit.
CMDSET
DETECT OPEN PDP CLR
Figure 5-62 Plasma Reset Circuit
Plasma interface signals
The five plasma interface signals are described as belows:
(1) *DATAO to DATA3
4-bit parallel display data signal. The dot lights when the
Signal line is low.
(2) *SFT CLK
Data transfer shift clock to shift display data into the shift
register.
(3) ¥*VS
Vertical sync signal. Moves scanning to the top display line.
(4) *HS
Horizontal sync signal. Generates a data strobe signal and
controls the l-line display drive circuit.
(5) *PDP CLR
Operation inhibit signal. When this signal is low, the anode
driver is turned off, the display is disabled.
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