Microprocessor Peripheral Circuits - Panasonic JB-3300 Technical Manual

CPU
This system uses a 8088 microprocessor (MPU).
The 8088 has two operation modes -- minimum and maximum. This system uses
the 8088 in the maximum mode, and operates the MPU clock at 4.77 MHz.
For details, see the data sheet attached to this manual.
Microprocessor Peripheral Circuits
Peripheral circuits, located in the periphery of he MPU 8088, are the MPU
bus controller, address latch circuit, data bus circuit, and wait state
generation circuit.
(a)
MPU bus controller
A MPU bus controller, which generates MPU bus control signals, is
required to operate the MPU 8088 in the maximum mode. This system
uses the 8288 as the MPU bus controller.
The MPU bus controller refers to the control status signals (*S2 to
*SO) output by the MPU, and produces the following control signals.
o ALE ..... Address latch enable signal (ALE)
Oo DEN ..... Data enable signal (DEN)
o DT/R.... Data transfer direction control Signal (DT/R)
o *MEMW ... Memory write signal (AMWC)
o *MWTC ... Memory write timing signal (MWTC)
Oo *MEMR ... Memory read signal (MRDC)
o *ITOW .... I/O write signal (ATOWC)
o *IOR .... I/O read signal (IORC)
o *INTA ... Interrupt acknowledge signal (INTA)
The MCE/PDEN and IOWC signals output by the 8288 are not used by this
system.
In the DMA cycle, the MPU bus controller sets up the command signals
*MEMW, *MWTC, *MEMR, *IOW, *IOR, and *INTA in a high impedance state
and changes the DEN signals to inactive (LOW) with the *AEN and
*AENCPU input signals.
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