Panasonic JB-3300 Technical Manual page 210

(2)
Data read
When all serial data (8 bits) is input, the first data enters
the interrupt request block and interrupts the CPU. The 8-bit
data is then read into the CPU as parallel data.
During the interrupt request, the clock pulses being input to he
serial/parallel conversion block are held LOW and stabilize the
data in this block.
At this time, the data line reset block holds *KBDATA line of
the L level, and disables this signal.
When the CPU finishes reading data through 8255-5, the CPU sets,
through 8255-5, PB7 to the L level, resets the interrupt request
block and the serial/parallel conversion block, sets *KBDATA to
the H level to keep it in the ENABLE state, and prepares for the
next data transfer.
When power is supplied, the 8255-5's output PB6 is set to the L
level according to the programmed condition, and *KBCLOCK goes
to L. With this signal, the keyboard performs self diagnosis.
When no key is pressed, the keyboard outputs OO to notify the
CPU of the normal condition. If it is abnormal, it transfers an
error code. The PB2 is in the service condition so that the CPU
can use the data line.
The I.C.P. protects against current surge if a short-circuit
occurs in the keyboard power line.
1) Keyboard timing at power on
*KBDATA Wn
nRBEBOK LF nl
40 ms min.
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