Panasonic JB-3300 Technical Manual page 172

(d) Status gate
The 4-bit status gate reads the status of the CRTC (HSYNC and VSYNC
states).
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DBO Lseaay|sync
DB1
DB2 yal wey
DB3 }———____ SYNC
*CRTD CS x
*XIOR —c
AEN —<
Figure 5-26 Status Gate Circuit
The status gate is enabled when it is read by the CPU. The states of
the status register is as follows:
DBO: HSYNC
DB1: Always LOW
DB2: Always HIGH
DB3: VSYNC
HS YNC
|
J
VSYNC TO
_ Se
Figure 5-27 Status Gate Timing Chart
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