Panasonic JB-3300 Technical Manual page 179

(h) Timing generator
The timing generator generates and controls basic timing of the
display circuit, CRTC clock pulses, VRAM access timing, RAS signal,
and CAS signal. The following paragraphs describe the circuits that
make up the timing generator block.
(1) Basic timing generator
The basic timing generator generates the clock pulses CLKI1 to
CLK4 (one eighth of the oscillator frequency) and the SHIFT
clock pulse from the oscillator frequency (18.432 MHz). The
generator also provides the RSCLK clock pulse (one tenth of the
oscillator frequency) to the 8251.
Figure 5-34 shows the basic timing generator circuit and Figure
5-35 shows the signal timing.
Osc
18.432MHz
| S175
D Q
q
D Q
11Q @
q
© D Q
BSCLK Q
D Q
0
CLK
(1-100) XRESET J
3 BASIC -CLK (7F)
(7-4E)
(7-7F)
Le
LSSi(
iP
> ¥CLK4
172)
CLK 1(4H)(7F )(7-1E)
%CLK 1(7G)(1C) (5-60)(7-1A)(7-1G)
CLK2(I1C)(7E)
*%CLK2 (7E)
CLK3(7G)
*CLK3(ID)(7G)(4E)
CLK4(7E)
[SHIFT]
$175(1 /4)
BASIC-CLK ——
0D Q SHIFT(7-1A)
> (7-3E)
10Q
Figure 5-34 Timing Generator Circuit
II - 59
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