Panasonic JB-3300 Technical Manual page 235

Table 5-13 Option Slot Connector Signal Description (2/3)
Signal
I/O
Description
*MEMR ©
Memory read line: Active low, memory read signal.
Data from memory must be placed on the data bus
while this line is low. This signal is issued
from the processor, or DMA controller.
* MEMW
Memory write line: Active low, memory write
control signal. Data on the data bus must be
written into memory while this line is low.
This signal is issued from the processor or DMA
controller.
*IOR
I/O read line: Active low, I/O read control
Signal. While this line is low, the addressed
I/O device places its data on the data bus.
This signal is issued from the processor or DMA
controller.
* TOW I/O write line: Active low, I/O write control
Signal. While this line is low, the addressed
I/O device reads the data from the data bus.
This signal is issued from the processor or DMA
controller.
RESET
Reset: Active high signal synchronized with a
falling/leading edge of the processor clock.
Turning the power on activates the RESET line to
provide initial reset to the circuitry.
The RESET signal remains active until the +5 V
supply line is completely stabilized.
OSC Oscillator: This is a high-speed 70 ns clock
with 50% duty cycle.
The frequency is 14.31818 MHz.
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