Panasonic JB-3300 Technical Manual page 145

+5
oa LS5I
LSI74
(X4E) ALE > is > XPADVNC (X3F)(X8E)
8
(X6A)S2 >—L4! SG 4 pb 8 5
(X10D0) ENDDMA D Q
D Q
6G
DQ
D @
D Q
(X3A) CLK > 3 cL
LSI75
d 68
Gq
dD 6@
6H Q
D Q
Udzi> 2 13 Q
_ Tso4 Ieab!
(X2C) XCLK >
°
x ap
> XYADVNC (KIB)(X3F)
(X10C)
XAENDMA
(XIOE)CENCPU
(KIOE) XADVNC
(X10C) XPADVNC
Figure 5-6 Timing Adjusting Circuit
Since the level of the status signal S2 is LOW when the MPU issues an
T/O command, the levels of the ALE signal (ENDDMA signal immediately
after a DMA cycle), as well as those of the *PADVNC and *ADVNC
Signals, go LOW one by one at each MPU clock pulse, and command
Signals are controlled by the input to the GBA pin of the
bi-directional buffer (LS243).
The command signals *XMEMR, *XMEMW, *XIOW, and *XIOR are output by
the trailing edge of the T2 clock cycle.
When memory or I/O access is slower than MPU operation, or when DMA
is in progress, a wait state has to be requested from the MPU. This
is another function of the wait state generation circuit.
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