Panasonic JB-3300 Technical Manual page 157

(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(1)
(3)
(k)
The DREQ signal requesting DMA is input to the relevant channel.
The DMAC monitors the DREQ signal and outputs the HRO signal to the
MPU hold control circuit to obtain the bus use right.
The MPU hold control circuit monitors the MPU bus usage at all times.
If the MPU is using the bus, the circuit holds the current status.
If the MPU is not using the bus, the circuit returns a hold answer
Signal (HLDA) to the DMAC.
The MPU hold control circuit returns HLDA in synchronization with the
MPU clock, and synchronizes and outputs the following signals.
Oo *AENCPU (MPU is using bus) HIGH level during DMA cycle
o *AENDMA (DMAC is using bus) LOW level during DMA cycle
Oo *AEN (DMA cycle) LOW level during DMA cycle
oO DMAWAIT (DMA cycle wait) HIGH level during DMA cycle
The *AENCPU and *AEN signals output by the MPU hold control circuit
releases the MPU address bus and data bus, establishing a high
impedance state. At the same time, the *MEMR, *MEMW, *IOR, and *IOW
command signals are inhibited.
When the MPU attempts to use the bus during a DMA cycle, the DMAWAIT
Signal is sent to set up a wait state until the DMA cycle is
finished. ,
The DMAC sends a DMA address when the HLDA signal is returned. The
upper eight bits of the DMA are sent to the data bus and latched by
the address strobe signal (ADSTB).
*DACK is sent to the I/O that issued the DMA request.
Then, the memory read/write signal (*XMEMR/*XMEMW) and I/O write/read
Signal (*XIOW/*XIOR) are output, and data transfer occurs between the
memory and the I/O.
If the DMA request is from an I/O other than Channel O (= refresh
request), the DMAWAIT control circuit processes the DMARDY signal and
produces a two-clock wait in the DMA cycle.
When DMA transfer finishes, the DREQ signal from the I/O is reset,
and relevant signals are reset one by one in the MPU hold control
circuit, in synchronization with the MPU clock, returning the bus use
right to the MPU. When the DMA cycle ends, the MPU hold control
circuit generates an ENDDMA signal to notifv the MPU peripheral
circuit of the end of the DMA cycle.
Figure 5-17 outlines DMA operating timing.
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