Panasonic JB-3300 Technical Manual page 224

Main System
DO7 to DOO
*FDDCS
*XIOW
*RESET
*TC
*DACK2
*DMAGATE
PCLK (9.54M)
DREQ2
IRQ6
DB7 to DBO
*XIOW
*XIOR
*FDCCS
XAB
Decoder
Decoder
ST
DREQ Controller
1.26 y
Delay
Data Block
FCC COMMAND 5 ~ *DRIVE SELI
Reg. Buffer = *DRIVE SEL2
j = *DRIVE SEL3
RST - *DRIVE SEL4
ed *MOTOR ON
Foc Buffer
wit C RST
INDEX} ~ * INDEX
21 X DACK
RW/SEEK
Y Decoder
oO WPRTT " *WRITE PROTECT
"TRK OO = Buffer
*TRACKOO
Buffer
SIDE —— *SIDE SEL
INT
DIR _ *DIRECTION
_IT4 ~| *STEP
07
La
| *WRITE DATA
DO WOA GATE
XWR WE ——— a *WRITE GATE
PSO
XRD
PSI BLOCK
cs *READ DATA
4m| PRECOMPESATION
AO
CLK O1
WCLK E Buffer
WINDOW
ROATA
ROAIAL—]
a.
SYNC __ I
MFM
DRQ
XG Voltage Detection
VFO
16H Clock Generator
Figure 5-74 Floppy Disk Interface Block Diagram