Q_Py_Pci_Pmon_Pkt_Match1 Registers; Q_Py_Pci_Pmon_Pkt_Match0 Registers - Intel Xeon E5-2600 Series Monitoring Manual

Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
Table 2-88. Q_Py_PCI_PMON_PKT_MATCH1 Registers
Field
---
RDS
---
RNID_3_0
Table 2-89. Q_Py_PCI_PMON_PKT_MATCH0 Registers
Field
RNID_4
---
DNID
MC
OPC
VNW
---
Reference Number: 327043-001
HW
Bits Reset
Val
31:20 0x0 Reserved; Must write to 0 else behavior is undefined.
19:16 0x0 Response Data State (valid when MC == DRS and Opcode == 0x0-
2). Bit settings are mutually exclusive.
b1000 - Modified
b0100 - Exclusive
b0010 - Shared
b0001 - Forwarding
b0000 - Invalid (Non-Coherent)
15:4 0x0 Reserved; Must write to 0 else behavior is undefined.
3:0 0x0 Remote Node ID(3:0 - Leat Significant Bits)
HW
Bits Reset
Val
31 0x0 Remote Node ID(Bit 4 - Most Significant Bit)
30:18 0x0 Reserved; Must write to 0 else behavior is undefined.
17:13 0x0 Destination Node ID
12:9 0x0 Message Class
b0000 HOM - Requests
b0001 HOM - Responses
b0010 NDR
b0011 SNP
b0100 NCS
---
b1100 NCB
---
b1110 DRS
8:5 0x0 Opcode
DRS,NCB:
[8] Packet Size, 0 == 9 flits, 1 == 11 flits
NCS:
[8] Packet Size, 0 == 1 or 2 flits, 1 == 3 flits
See Section 2.10, "Packet Matching Reference"
opcodes that may be filtered per message class.
4:3 0x0 Virtual Network
b00 - VN0
b01 - VN1
b1x - VNA
2:0 0x0 Reserved; Must write to 0 else behavior is undefined.
Description
Description
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