Imc Performance Monitoring Events; An Overview; Mc_Chy_Pci_Pmon_Fixed_Ctl Register - Field Definitions; Mc_Chy_Pci_Pmon_Ctr{Fixed,3-0} Register - Field Definitions - Intel Xeon E5-2600 Series Monitoring Manual

All MC performance monitor data registers are 48-bit wide. Should a counter overflow (a carry out
from bit 47), the counter will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
This is a counter that always tracks the number of DRAM clocks (dclks - half of DDR speed) in the iMC.
The dclk never changes frequency (on a given system), and therefore is a good measure of wall clock
(unlike the Uncore clock which can change frequency based on system load). This clock is generally a
bit slower than the uclk (~800MHz to ~1.066GHz) and therefore has less fidelity.
Table 2-62. MC_CHy_PCI_PMON_FIXED_CTL Register – Field Definitions
Field
rsv
rsv
en
rsv
rst
rsv
Table 2-63. MC_CHy_PCI_PMON_CTR{FIXED,3-0} Register – Field Definitions
Field
rsv
event_count
2.5.5

iMC Performance Monitoring Events

2.5.5.1

An Overview:

A sampling of events available for monitoring in the iMC:
• Translated commands: Various Read and Write CAS commands
• Memory commands: CAS, Precharge, Refresh, Preemptions, etc,
• Page hits and page misses.
• Page Closing Events
• Control of power consumption: Thermal Throttling by Rank, Time spent in CKE ON mode,
etc.
and many more.
Internal iMC Queues:
62
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
HW
Bits Attr Reset
Val
31:24 RV 0 Reserved (?)
23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
22 RW-V 0 Local Counter Enable.
21:20 RV 0 Reserved. SW must write to 0 else behavior is undefined.
19 WO 0 When set to 1, the corresponding counter will be cleared to 0.
18:0 RV 0 Reserved (?)
HW
Bits Attr Reset
Val
63:48 RV 0 Reserved (?)
47:0 RW-V 0 48-bit performance event counter
Description
Description
Reference Number: 327043-001