Power Control (Pcu) Performance Monitoring; Overview Of The Pcu; Pcu Performance Monitoring Overview; Pcu Performance Monitors - Intel Xeon E5-2600 Series Monitoring Manual

2.6

Power Control (PCU) Performance Monitoring

2.6.1

Overview of the PCU

The PCU is the primary Power Controller.
The uncore implements a power control unit acting as a core/uncore power and thermal manager. It
runs its firmware on an internal micro-controller and coordinates the socket's power states.
The PCU algorithmically governs the P-state of the processor, C-state of the core and the package C-
state of the socket. It also enables the core to go to a higher performance state ("turbo mode") when
the proper set of conditions are met. Conversely, the PCU will throttle the processor to a lower
performance state when a thermal violation occurs.
Through specific events, the OS and the PCU will either promote or demote the C-State of each core
by altering the voltage and frequency. The system power state (S-state) of all the sockets in the
system is managed by the server legacy bridge in coordination with all socket PCUs.
The PCU communicates to all the other units through multiple PMLink interfaces on-die and Message
Channel to access their registers. The OS and BIOS communicates to the PCU thru standardized MSR
registers and ACPI.
The PCU also acts as the interface to external management controllers via PECI and voltage
regulators (NPTM). The DMI interface is the communication path from the southbridge for system
power management.
Note: Many power saving features are tracked as events in their respective units. For
example, Intel® QPI Link Power saving states and Memory CKE statistics are captured
in the Intel® QPI Perfmon and iMC Perfmon respectively.
2.6.2

PCU Performance Monitoring Overview

The uncore PCU supports event monitoring through four 48-bit wide counters
(PCU_MSR_PMON_CTR{3:0}). Each of these counters can be programmed
(PCU_MSR_PMON_CTL{3:0}) to monitor any PCU event. The PCU counters can increment by a
maximum of 4b (?) per cycle.
Two extra 64-bit counters are also provided in the PCU to track C-State Residency. Although
documented in this manual for reference, these counters exist outside of the PMON infrastructure.
For information on how to setup a monitoring session, refer to
Performance Monitoring Control"
2.6.3

PCU Performance Monitors

Table 2-73. PCU Performance Monitoring MSRs (Sheet 1 of 2)
Generic Counters
PCU_MSR_PMON_CTR3
PCU_MSR_PMON_CTR2
PCU_MSR_PMON_CTR1
72
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
.
MSR Name
Section 2.1, "Uncore Per-Socket
MSR Size
Address (bits)
0x0C39 64 PCU PMON Counter 3
0x0C38 64 PCU PMON Counter 2
0x0C37 64 PCU PMON Counter 1
Description
Reference Number: 327043-001