R3Qpi Performance Monitors; R3Qpi Box Level Pmon State; R3Qpi Performance Monitoring Registers; R3_Ly_Pci_Pmon_Box_Ctl Register - Field Definitions - Intel Xeon E5-2600 Series Monitoring Manual

2.9.3

R3QPI Performance Monitors

Table 2-118. R3QPI Performance Monitoring Registers
PCICFG Base Address
R3QPI Link 0 PMON Registers
R3QPI Link 1 PMON Registers
Box-Level Control/Status
R3_Ly_PCI_PMON_BOX_CTL
Generic Counter Control
R3_Ly_PCI_PMON_CTL2
R3_Ly_PCI_PMON_CTL1
R3_Ly_PCI_PMON_CTL0
Generic Counters
R3_Ly_PCI_PMON_CTR2
R3_Ly_PCI_PMON_CTR1
R3_Ly_PCI_PMON_CTR0
2.9.3.1

R3QPI Box Level PMON State

The following registers represent the state governing all box-level PMUs for each Link of the R3QPI
Box.
In the case of the R3QPI Links, the R3_Ly_PCI_PMON_BOX_CTL register governs what happens when
a freeze signal is received (.frz_en). It also provides the ability to manually freeze the counters in the
box (.frz) and reset the generic state (.rst_ctrs and .rst_ctrl).
Table 2-119. R3_Ly_PCI_PMON_BOX_CTL Register – Field Definitions
Field
rsv
rsv
frz_en
rsv
frz
rsv
rst_ctrs
rst_ctrl
U
120
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
Register Name
HW
Bits Attr Reset
Val
31:18 RV
17 RV
16 WO
15:9 RV
8 WO
7:2 RV
1 WO
0 WO
PCICFG Size
Address (bits)
Dev:Func
D19:F5
D19:F6
F4 32 R3QPI Link y PMON Box-Wide Control
E0 32 R3QPI Link y PMON Control for Counter 2
DC 32 R3QPI Link y PMON Control for Counter 1
D8 32 R3QPI Link y PMON Control for Counter 0
B4+B0 32x2 R3QPI Link y PMON Counter 2
AC+A8 32x2 R3QPI Link y PMON Counter 1
A4+A0 32x2 R3QPI Link y PMON Counter 0
Description
0 Reserved (?)
0 Reserved; SW must write to 0 else behavior is undefined.
0 Freeze Enable.
If set to 1 and a freeze signal is received, the counters will be
stopped or 'frozen', else the freeze signal will be ignored.
0 Reserved (?)
0 Freeze.
If set to 1 and the .frz_en is 1, the counters in this box will be
frozen.
0 Reserved (?)
0 Reset Counters.
When set to 1, the Counter Registers will be reset to 0.
0 Reset Control.
When set to 1, the Counter Control Registers will be reset to 0.
Description
Reference Number: 327043-001