Intel® Qpi Ll Box Performance Monitor Event List - Intel Xeon E5-2600 Series Monitoring Manual

Table 2-95. Metrics Derived from Intel QPI LL Events (Sheet 3 of 3)
PCT_LINK_FULL_POWER_CYCLES:
Percent of Cycles the QPI link is at Full
Power
PCT_LINK_HALF_DISABLED_CYCLES:
Percent of Cycles the QPI link in power
mode where half of the lanes are disabled.
PCT_LINK_SHUTDOWN_CYCLES:
Percent of Cycles the QPI link is Shutdown
QPI_LINK_UTIL:
Percentage of cycles that QPI Link was
utilized. Calculated from 1 - Number of idle
flits - time the link was 'off'
QPI_SPEED:
QPI Speed - In GT/s (GigaTransfers /
Second) - Max QPI Bandwidth is 2 * ROUND
( QPI Speed , 0)
2.7.7 Intel® QPI LL Box Performance Monitor Event List
The section enumerates the performance monitoring events for the Intel® QPI LL Box.
CLOCKTICKS
• Title: Number of qfclks
• Category: CFCLK Events
• Event Code: 0x14
• Max. Inc/Cyc: 1, Register Restrictions: 0-3
• Definition: Counts the number of clocks in the Intel® QPI LL. This clock runs at 1/8th the "GT/s"
speed of the Intel® QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not sup-
port dynamic link speeds, so this frequency is fixed.
CTO_COUNT
• Title: Count of CTO Events
• Category: CTO Events
• Event Code: 0x38
• Extra Select Bit: Y
• Max. Inc/Cyc: 2, Register Restrictions: 0-3
• Definition: Counts the number of CTO (cluster trigger outs) events that were asserted across the
two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge
detect to count the number of cases when both events triggered.
DIRECT2CORE
• Title: Direct 2 Core Spawning
• Category: DIRECT2CORE Events
• Event Code: 0x13
• Max. Inc/Cyc: 1, Register Restrictions: 0-3
• Definition: Counts the number of DRS packets that we attempted to do direct2core on. There are
4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the
different failure cases. Note that this does not count packets that are not candidates for
Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.
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Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
Symbol Name:
Definition
Equation
RxL0_POWER_CYCLES / CLOCKTICKS
RxL0p_POWER_CYCLES / CLOCKTICKS
L1_POWER_CYCLES / CLOCKTICKS
(RxL_FLITS_G0.DATA + RxL_FLITS_G0.NON_DATA) / (2 *
CLOCKTICKS)
ROUND ((CLOCKTICKS / (CLOCKTICKS * QPI_VALUES)) *
TSC_SPEED, 0 ) * ( 8 / 1000)
Reference Number: 327043-001