6.4 Supervision Configuration Registers
Index
0x30
0x60
0x61
Bit
7:01
0
Bit
15:03
2
FPGA Registers
For public disclosure
Supervision Configuration Registers
Name
Logical device activation control
Control
Supervision
Supervision registers base I/O address (upper 8 bits)
Base (High)
Supervision
Supervision registers base I/O address (lower 8 bits)
Base (Low)
6.4.1 Supervision Control
The Supervision Control register allows the logical device to be activated or deactivated.
Supervision Control Register (LDN 0x0A, Index 0x30)
Name
Access
—
R
ACTIVATE
R/W
6.4.2 Supervision Base Address
The Supervision Base Address register sets the I/O base address for the supervision
registers. The base address must be aligned on an 8-byte boundary.
Supervision Base Address Register (LDN 0x0A, Index 0x60-0x61)
Name
Access
ADDR[15:3]
R/W
—
R
Description
Description
Default
0b0000000
Reserved
Logical device activation
0
0: Disabled
1: Enabled
Description
Default
0x0000
Base address bits 15:03
0b000
Reserved
GFK-2896 Hardware Reference Manual 51
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