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Offset
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Bit
31:24
23:0
Bit
31:24
23:0
FPGA Registers
For public disclosure
6.9.7 Watchdog Timer Run-Time Registers
The Watchdog timer run-time registers are listed in the following table. The address
indicates the offset from the port base addresses programmed in the configuration
registers. The Watchdog timer is capable of timing intervals ranging from 8 μsec to over
128 seconds. It is clocked with a 33.33 MHz reference clock and a 125 kHz clock enable.
Upon being enabled or serviced, the Watchdog timer is loaded with the interrupt count
value, and then counts down by one every 8 μsec. If the counter reaches 0, it generates an
interrupt and automatically loads the reset count value. If the counter reaches 0 again, the
WDT signal is asserted, and if enabled, a non-maskable interrupt or a system reset is
issued.
Watchdog Timer Run-Time Registers
Name
Interrupt count lower byte
Int Count Low
Interrupt count middle byte
Int Count Mid
Int Count High
Interrupt count upper byte
—
Reserved
Reset count lower byte
Reset Count Low
Reset count middle byte
Reset Count Mid
Reset Count High
Reset count high byte
—
Reserved
Timer control register
Control
—
Reserved
Timer reload register
Reload
—
Reserved
Timer status register
Status
—
Reserved
Interrupt Enable
Interrupt Enable Register
—
Reserved
The interrupt and reset count register contents can be changed while the Watchdog timer
is unlocked, but the new values will not take effect until the Watchdog is serviced. The
actual timeout intervals are equal to the value in the count register plus 1, times 8 μsec.
Watchdog Interrupt Count Register (Offset 0x0-0x3)
Name
Access
—
R
INT_CNT[23:0]
R/W
Watchdog Reset Count Register (Offset 0x4-0x7)
Name
Access
—
R
RST_CNT[23:0]
R/W
Write access to any of the Watchdog timer registers must be preceded by a two-byte
sequence (0x17, 0x75) written to the control register address. After reset, the Watchdog is
disabled and unlocked. It may be freely enabled and disabled while it is unlocked. It may
also be freely locked and unlocked while it is disabled. If the Watchdog timer is locked
while it is enabled, it will remain in that state until it is reset.
Description
Description
Default
0x00
Reserved
Watchdog interrupt count
0xFFFFFF
value
Description
Default
0x00
Reserved
Watchdog reset count
0xFFFFFF
value
GFK-2896 Hardware Reference Manual 71
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