Interrupt Enable - GE Mini COM Express 10 Hardware Reference Manual

Bit
7
6
5
4
3
2
1
0
FPGA Registers
For public disclosure

6.7.3 Interrupt Enable

This register provides the means to enable or mask individual causes from generating an
external UART interrupt. When set to 0, the interrupt cause is masked. When set to 1, the
interrupt cause is enabled. Access to the DMA interrupt and transfer enable bits is
allowed only when DMA is enabled in the UART mode configuration register. Otherwise,
these bits are read-only and forced to zero.
UART Interrupt Enable Register (Offset 0x1)
Name Access Default
TX_XFR
R/W
RX_XFR
R/W
TX_DMA
R/W
RX_DMA
R/W
MODEM R/W
LINE R/W
TX R/W
RX R/W
Description
Transmit DMA transfer enable.
Automatically cleared when the
0
transfer is complete (as indicated
by the terminal count).
Receive DMA transfer enable.
Automatically cleared when the
0
transfer is complete (as indicated
by the terminal count).
Transmit DMA transfer complete
0
interrupt enable
Receive DMA transfer complete
0
interrupt enable
Modem status interrupt enable
0
Received line status interrupt
0
enable
Transmit holding register empty
0
interrupt enable
Received data available interrupt
0
enable
GFK-2896 Hardware Reference Manual 57