Bit
7:04
3
Bit
7:02
1:0
0
FPGA Registers
For public disclosure
6.6.3 Watchdog Timer IRQ
The Watchdog Timer IRQ register sets the interrupt request line used by the Watchdog
Timer.
Watchdog Timer IRQ Register (LDN 0x14, Index 0x70)
Name
Access
Default
—
R
0b0000
IRQ
R/W
0b0000
6.6.4 Watchdog Timer Options
The Watchdog Timer Options register controls the interrupt and reset outputs of the
Watchdog.
Name
Access
—
R
RST_EN
R/W
NMI_EN
R/W
Description
Reserved
Interrupt request line
assignment
0b0000: None
0b0001: IRQ1
0b0010: IRQ2
0b0011: IRQ3
0b0100: IRQ4
0b0101: IRQ5
0b0110: IRQ6
0b0111: IRQ7
0b1000: IRQ8
0b1001: IRQ9
0b1010: IRQ10
0b1011: IRQ11
0b1100: IRQ12
0b1101: IRQ13
0b1110: IRQ14
0b1111: IRQ15
Description
Default
0b000000
Reserved
0
Reset enable
Non-maskable interrupt
0
enable
GFK-2896 Hardware Reference Manual 55
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