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6 FPGA Registers
6.1 Configuration Access Port
Address
0x002E
0x002F
Bit
7:0
Bit
7:0
FPGA Registers
For public disclosure
The LPC bus hosts several functions: two UARTs, the board supervision controller, an
I
2
C bus controller, and a watchdog timer. These functions are configured through a bank
of registers indirectly accessed through a pair of I/O ports to configure the I/O address,
interrupt line, and operating parameters. Each function has its own set of run-time
registers accessed directly using I/O read and write cycles.
Access to the configuration registers is indirect through a pair of I/O ports, the index port
and the data port. After reset, all the configuration registers are locked and cannot be
accessed. Configuration register access is enabled by writing an unlock code, 0x78, to the
Index port address. Subsequently, configuration register access can be disabled again by
writing a lock code, 0x87, to the Index port address. The lock and unlock codes do not
match any internal index addresses.
Configuration Access Port
Name
Configuration register index pointer
Index
Configuration data access
Data
6.1.1 Index Port
The Configuration Index register is an 8-bit read/write register used as a pointer into the
configuration register file. It contains the index of the configuration register that is
accessed through the data port.
Configuration Index Register (Address 0x002E)
Name
Access
INDEX
R/W
6.1.2 Data Port
The Configuration Data register is an 8-bit virtual register used for the data path to the
configuration register pointed to by the Index register. It writes or reads to and from the
Data Port access the actual configuration register.
Configuration Data Register (Address 0x002F)
Name
Access
Default
DATA
R/W
Description
Description
Default
Pointer to configuration register index
0x00
Description
Data to/from indexed configuration
—
register
GFK-2896 Hardware Reference Manual 45
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