Bit
7:05
4:0
LOOPBACK
3:0
2:0
1:0
0:0
FPGA Registers
For public disclosure
6.7.7 Modem Control
This register controls the UART interface to a modem.
UART Modem Control Register (Offset 0x4)
Name
Access
Default
—
R
R/W
OUT2
R/W
OUT1
R/W
RTS
R/W
DTR
R/W
Description
0b000
Reserved
Loop-back mode
0: Normal operation
1: Loop-back operation. In this mode, the
serial transmit output is set to 1, the transmit
0
shift register is internally connected to the
receive shift register, DTR is connected to
DSR, RTS is connected to CTS, OUT1 is
connected to RI, and OUT2 is connected to
DCD.
Output 2. In Loop-back mode, connected to
0
Data Carrier Detect input.
Output 1. In Loop-back mode, connected to
0
Ring Indicator input.
External Request To Send signal control
0
0: RTS is set to 1
1: RTS is set to 0
External Data Terminal Ready signal control
0
0: DTR is set to 1
1: DTR is set to 0
GFK-2896 Hardware Reference Manual 61
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