C Controller Run-Time Registers; Clock Prescale - GE Mini COM Express 10 Hardware Reference Manual

6.9 I 2

C Controller Run-Time Registers

Offset
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Bit
7:0
Bit
7:0
FPGA Registers
For public disclosure
I 2 C controller run-time registers are listed in the following table. The address indicates the
offset from the port base addresses programmed in the configuration registers.
I 2 C Controller Run-Time Registers
Name
Prescale (low byte)
Prescale (high byte)
Control
Receive
Transmit
Status
Command
Transmit (read back)
Command (read back)
Reserved

6.9.1 Clock Prescale

The I 2 C clock frequency is set by a 16-bit prescale value. The actual frequency is equal to
the FPGA core clock (33.33 MHz) divided by five times the prescale value (plus one).
For example, a prescale value of 0x42 yields an I
prescale value of 0x10 yields an I
I 2 C Clock Prescale (LSB) Register (Offset 0x0)
Name Access
PRESCALE[7:0]
R/W
I 2 C Clock Prescale (MSB) Register (Offset 0x1)
Name Access
PRESCALE[15:8]
R/W
Description
Clock prescale – least-significant byte
Clock prescale – most-significant byte
Control register
Receive data (read)
Transmit data (write)
Status register (read)
Command register (write)
Transmit data (read)
Command register (read)
Reserved
2
C clock frequency of 99.5 kHz, and a
2
C clock frequency of 392.2 kHz.
Description
Default
LSB of baud-rate
0xFF
generator divisor
Description
Default
MSB of baud-rate
0xFF
generator divisor
GFK-2896 Hardware Reference Manual 67