GE Mini COM Express 10 Hardware Reference Manual page 13

User
EeeP
DDR3 L
2 /4/8GB
ECC
SPD
Debug
Introduction
For public disclosure
G-Series SoC
CPU Core
CPU Core
CPU Core
CPU Core
L1 Cache
L1 Cache
L1 Cache
L1 Cache
L2 Cache
North Bridge
GPU
SMBus
South Bridge
mCOM10-L1500 Functional Block Diagram
FPGA
Supv
UART
UART
I2C
WDog
VGA
PCIe
I210
Flash
GFK-2896 Hardware Reference Manual 13
Ser0
Ser1
I2C
WDT
LVDS/eDP
DDI0
GbE0
LPC
PCIe[0:3]
2x SATA
8x USB
2x USB_SS
HDA
GPIO/SD
SPI
SMBus