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Bit
7:02
1:0
0:0
Bit
7:01
0:0
Bit
7:02
1:0
0:0u
Bit
7:01
0:0
72
GFK-2896
For public disclosure
Watchdog Timer Control Register (Offset 0x8)
Name
Access
—
R
LOCK
R/W
EN
R/W
The Reload register provides a means to service the Watchdog timer while it is enabled.
Watchdog Timer Reload Register (Offset 0xA)
Name
Access
—
R
RELOAD
R/W
The Status register indicates whether the Watchdog interrupt and reset timers have
expired. The reset indication is a sticky bit that is not cleared on a system reset, although
it is cleared on powerup.
Watchdog Timer Status Register (Offset 0xC)
Name
Access
—
R
EXP_RST
R/C
EXP_SERIRQ
R/C
Watchdog Timer Interrupt Enable Register (Offset 0xE)
Name
Access
—
R
EN_SERIRQ
RW
Description
Default
0x00
Reserved
Watchdog timer lock
0
0: Unlocked
1: Locked
Watchdog timer enable
0
0: Disabled
1: Enabled
Description
Default
0x00
Reserved
Writing a 1 reloads the
Watchdog timer with the value
0
in the Interrupt Count register.
Always reads back 0.
Description
Default
0b000000
Reserved
Reset timer expired. When
1, indicates that the
Watchdog reset timer has
expired. Cleared by writing
0
a 1 to the bit. Sticky bit that
retains its value through a
system reset.
SERIRQ timer expired.
When 1, indicates that the
Watchdog timer has
0
expired an issued an
interrupt. Cleared by writing
a 1 to the bit.
Description
Default
0b0000000
Reserved
Enable SERIRQ
0
1 = Enable SERIRQ
0 = Disable SERIRQ
Mini COM Express Type 10 Module mCOM10-L1500
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