Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual
  1. Manuals
  2. Brands
  3. Xilinx Manuals
  4. Control Unit
  5. Kintex UltraScale FPGA KCU1250
  6. Getting started manual
Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual

Xilinx Kintex UltraScale FPGA KCU1250 Getting Started Manual

Characterization kit ibert
Hide thumbs Also See for Kintex UltraScale FPGA KCU1250:
Table of Contents

Advertisement

Quick Links

Download this manual
Kintex UltraScale FPGA
KCU1250
Characterization Kit
IBERT
Getting Started Guide
Vivado Design Suite
UG1061 (v2016.1) April 13, 2016

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Kintex UltraScale FPGA KCU1250 and is the answer not in the manual?

Questions and answers

Related Manuals for Xilinx Kintex UltraScale FPGA KCU1250

Summary of Contents for Xilinx Kintex UltraScale FPGA KCU1250

  • Page 1 Kintex UltraScale FPGA KCU1250 Characterization Kit IBERT Getting Started Guide Vivado Design Suite UG1061 (v2016.1) April 13, 2016...

  • Page 2: Revision History

    Updated for Vivado Design Suite 2015.2. Design file rdf0352-kcu1250-ibert-2015-1.zip changed to rdf0352-kcu1250-ibert-2015-2.zip. Board power on was added to step 3, page 13. Updated Figure 2-2, Figure 2-4, and Figure 2-8. Initial Xilinx release. 04/27/2015 2015.1 KCU1250 IBERT Getting Started Guide www.xilinx.com UG1061 (v2016.1) April 13, 2016...

  • Page 3: Table Of Contents

    Xilinx Resources ........

  • Page 4: Overview

    Starting the SuperClock-2 Module, page 12 Configuring the FPGA, page 15 Setting Up the Vivado Design Suite, page 17 Viewing GTH Transceiver Operation, page 23 Closing the IBERT Demonstration, page 24 KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 5: Requirements

    The hardware and software required to rebuild the IBERT demonstration designs are: • Xilinx Vivado Design Suite 2016.1 • PC with a version of the Windows operating system supported by Xilinx Vivado Design Suite Setting Up the KCU1250 Board This section describes how to set up the KCU1250 board.

  • Page 6: Extracting The Project Files

    The Vivado Design Suite BIT files required to run the IBERT demonstrations are located in rdf0352-kcu1250-ibert-2016-1.zip on the SD card provided with the KCU1250 board. The BIT files are also available online at the Kintex UltraScale FPGA KCU1250 Characterization Kit documentation website.

  • Page 7: Running The Gth Ibert Demonstration

    QUAD 131 and QUAD 132 are not available on the XCKU040 device. Note: X-Ref Target - Figure 1-1 QUAD_224 QUAD_225 QUAD_226 QUAD_227 QUAD_228 QUAD_131 QUAD_132 Figure 1-1: GTH Quad Locations KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 8 LVDS clock output from the Si570 programmable oscillator on the clock module. The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the Note: SuperClock-2 module. KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 9 X-Ref Target - Figure 1-5 Figure 1-5: BullsEye Connector Attached to Quad 224 KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 10 To ensure good connectivity, it is recommended that the adapters be secured with a wrench; Note: however, do not over-tighten the SMAs. X-Ref Target - Figure 1-6 Figure 1-6: SMA F-F Adapter KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 11 KCU1250 board with the cable connections required for the Quad 224 GTH IBERT demonstration. X-Ref Target - Figure 1-8 Figure 1-8: Cable Connections for Quad 224 GTH IBERT Demonstration KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 12: Starting The Superclock-2 Module

    Outputs from either source can be used to drive the transceiver reference clocks. To start the SuperClock-2 module: 1. The SuperClock-2 module is configured using the Xilinx XC7Z010CLG225 Zynq-7000APSoC System Controller command line which can be accessed through a serial communication terminal connection using the enhanced communication port of...
  • Page 13 Silicon Lab USB-UART Bridge. Set up a new connection as in Figure 1-12, and press the Return key to connect and view the System Controller options menu. X-Ref Target - Figure 1-12 Figure 1-12: Terminal Setting KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 14 5. View KCU1250 Saved Clocks in EEPROM 6. Set KCU1250 Clock Restore Options 7. Read KCU1250 Si570 Frequency 8. Read KCU1250 Si5368 Frequency 0. Return to Main Menu Select an option KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 15: Configuring The Fpga

    2 - Free-Run using XA-XB crystal Configuring the FPGA The KCU1250 board additionally utilizes the Xilinx XC7Z010CLG225 Zynq-7000 AP SoC System Controller to implement a System Integrated Configuration Engine (System ICE) to configure the FPGA using one of the configuration *.bit files provided on the SD card in 8-bit SMAP configuration mode.
  • Page 16 4. Select option (0) to configure the FPGA with the Quad 224 IBERT example design. Press Enter and review the terminal for configuration progress: Enter a Bitstream number (0-15): Info : xilinx.sys opened Info : Opening rev_1/set0/config.def Info : Configuration definition file "rev_1/set0/config.def"...

  • Page 17: Setting Up The Vivado Design Suite

    U80, the Digilent USB JTAG configuration port on the KCU1250 board (Figure 1-13). X-Ref Target - Figure 1-13 Figure 1-13: USB-UART Connector KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 18 2. Start the Vivado Design Suite on the host computer and click Flow > Open Hardware Manager (highlighted in Figure 1-14). X-Ref Target - Figure 1-14 Figure 1-14: Vivado Design Suite, Open Hardware Manager KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 19 4. An Open Hardware Target wizard opens. Click Next in the first window. 5. In the Hardware Server Settings window, select Local server (target is on local machine). Click Next. KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 20 Design Suite default warnings and notifications setting has not been changed. Press Yes to automatically detect the links (Figure 1-17). X-Ref Target - Figure 1-17 Figure 1-17: Auto-Detect the Serial I/O Links KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 21 Create Links or by clicking the Create Links button (Figure 1-18). X-Ref Target - Figure 1-18 Figure 1-18: Serial I/O Analyzer – Create Links KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 22 MGT_X0Y1/TX (xcku040_0/Quad_224) to MGT_X0Y1/RX (xcku040_0/Quad_224) ° MGT_X0Y2 /TX (xcku040_0/Quad_224) to MGT_X0Y2/RX (xcku040_0/Quad_224) ° MGT_X0Y3/TX (xcku040_0/Quad_224) to MGT_X0Y3/RX (xcku040_0/Quad_224) ° X-Ref Target - Figure 1-19 Figure 1-19: Create Links Window KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 23: Viewing Gth Transceiver Operation

    Click the respective TX Reset button followed by BERT Reset. Additional information on the Vivado Design Suite and IBERT core can be found in Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 24: Closing The Ibert Demonstration

    To stop the IBERT demonstration: 1. Close the Vivado Design Suite by selecting File > Exit. 2. Place the main power switch SW1 in the OFF position. KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 25: Chapter 2: Creating The Gth Ibert Core

    2. In the Vivado Design Suite window, click Manage IP (highlighted in Figure 2-1) and select New IP Location. X-Ref Target - Figure 2-1 Figure 2-1: Vivado Design Suite Initial Window KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 26 Part field. A Select Device window is displayed. Use the drop-down menu items to narrow the choices. Select the xcku040-ffva1156-3-e device (see Figure 2-2). Click OK. X-Ref Target - Figure 2-2 Figure 2-2: Select Device KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 27 IP (Figure 2-3). Click Finish. Make sure the directory name does not include spaces. Note: X-Ref Target - Figure 2-3 Figure 2-3: Manage IP Settings KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 28 6. In the IP Catalog window, expand the Debug & Verification folder, expand the Debug folder, and double-click IBERT UltraScale GTH (Figure 2-4). X-Ref Target - Figure 2-4 Figure 2-4: IP Catalog KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 29 12.5 Gbps. Change Refclk (MHz) to 125. Keep defaults for other fields (Figure 2-5). X-Ref Target - Figure 2-5 Figure 2-5: Customize IP – Protocol Definition KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 30 8. In the Protocol Selection tab, use the Protocol Selected drop-down menu next to QUAD_224 to select Custom 1/12.5 Gb/s (Figure 2-6). X-Ref Target - Figure 2-6 Figure 2-6: Customize IP – Protocol Selection KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 31 (Figure 2-7). Click OK. Click Generate in the next window to generate the output products. X-Ref Target - Figure 2-7 Figure 2-7: Customize IP - Clock Settings KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 32 2-8). Specify a location to save the design, click OK, and the design opens in a new Vivado Design Suite window. X-Ref Target - Figure 2-8 Figure 2-8: Open IP Example Design KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 33 11. In the Sources window, Design Sources should now show the IBERT design example (Figure 2-9). X-Ref Target - Figure 2-9 Figure 2-9: Design Sources File Hierarchy KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 34 Creating the GTH IBERT Core 12. Click Run Synthesis from the Flow Navigator to synthesize the design (Figure 2-10). X-Ref Target - Figure 2-10 Figure 2-10: Run Synthesis KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 35 14. When the implementation is done, an Implementation Completed window opens. Select Generate Bitstream and click OK (Figure 2-12). X-Ref Target - Figure 2-12 Figure 2-12: Implementation Completed KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...
  • Page 36 15. When the Bitstream Generation Completed dialog window appears, click Cancel (Figure 2-13). X-Ref Target - Figure 2-13 Figure 2-13: Bitstream Generation Complete 16. Navigate to the ...\ibert_ultrascale_gth_0_example\ibert_ultrascale_gth_0_exampl e.runs\impl_1 directory to locate the generated bitstream. KCU1250 IBERT Getting Started Guide www.xilinx.com Send Feedback UG1061 (v2016.1) April 13, 2016...

  • Page 37: Appendix A: Additional Resources And Legal Notices

    Kintex UltraScale FPGA KCU1250 Characterization Kit Kintex UltraScale FPGA KCU1250 Characterization Kit documentation Kintex UltraScale FPGA KCU1250 Characterization Kit Master Answer Record (AR 63058) These Xilinx documents provide supplemental material useful with this guide: 1. KCU1250 Board User Guide (UG1057) 2.

  • Page 38: Please Read: Important Legal Notices

    Xilinx’s Terms of Sale which can be viewed at http://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...
  • Page 39 Customer. For any breach by Xilinx of this limited warranty, the exclusive remedy of Customer and the sole liability of Xilinx shall be, at the option of Xilinx, to replace or repair the affected products, or to refund to Customer the price of the affected products.

Table of Contents